Process Technology Will Deliver $3bn+, Growing, Digital IC Business, says ST's Chery.

STMicroelectronics will have a $3bn digital IC business next year based on superior IC process technology, says the company's CTO and CMO, Jean-Marc Chery.
 At ST's investor day in London yesterday, various analysts questioned the value of ST investing in advanced process technology nodes when the company's sales of products using those processes are low.
"This is incremental innovation," responded Chery, "not breakthrough innovation." He put the R&D cost of developing advanced processes and the IP to go with them at $300m a year.
That $300m development cost supports a number of digital businesses - ASIC, DSP, STB, cable modems, microcontrollers - which share the IP libraries.
Collectively these digital businesses will be drawing revenues of $3bn next year.
"We will have a $3bn business as from next year," said Chery, "and then we will start to grow."
Chery has a roadmap from 28nm, to 14nm, to 10nm - all of which will be planar with FD-SOI contributing the high-performance/low power processing.
Chery decides which products go into FD-SOI. So fsr,  the FD-SOI products include a high-complexity, low-power, low volume ASIC for networking, a high volume consumer ASIC, the Novar-Thor integrated apps processor and modem which is being sold by ST not for handsets but for other mobile applications, and the next FD-SOI product will be a DSP.
The planar FD-SOI process is going to be s huge deal for ST, reckons Chery. "Rather than a complicated technology like finfet this is well adapted to consumer electronics," he said, "customers don't want to pay the cost of finfet."
Chery has aggressive scaling plans for FD-SOI. "We have a PDK at 14nm and expect to have 14nm IP ready this year and will start to make test vehicles to qualify the process by the end of this year," said Chery, "14nm will be ready to prototype products in Q2 2014 - we must be ready with 14nm FD-SOI before anyone has finfet at 14nm."
"We can come down to 10nm planar - we have silicon demonstrating the readiness of the technology," said Chery, "our vision is that, at 7nm we will go in with finfet - not with bulk finfet - but with finfet-on-SOI. But, if we can extend planar to 7nm, we will do it."



  1. Well he did add that he’ll stay on planar if he can, Mike, and 7nm is three nodes, or nine years, in the future and even Gordon Moore said he had never been able to forecast process technology development for more than 18 months into the future

  2. I can sort of guess what it is, Mike, but the Crolles guys get help from lots of people – IBM of course for one, CEA-LETI, France Telecom, the French Government and assorted ecoles and intstituts all over France.

  3. So ST on $0.3bn per annum and no help from IMEC is going to out-develop TSMC spending $1.5bn per annum with the help of IMEC.

    There’s a word for this strategy ……………

  4. “our vision is that, at 7nm we will go in with finfet – not with bulk finfet – but with finfet-on-SOI.”

    So ST is going FinFET at the same node everyone else will be leaving it ? A remarkedly strange strategy.

  5. Well clearly he’s targetting the ASIC business which is essentislly design + foundry.

  6. Yes Dave, cost is good but in terms of volume, digital biz is dominated by Qualcomm/Broadcom/etc not ST. unless JM intends to use FD-SOI as a leverage to start foundry biz for ST.

  7. Well he’s got customers wanting it, Jack. Power/performance/density looks good. Cost is OK. That always used to be the recipe for success in the IC business.

  8. This is a huge gamble, knowing digital biz on ST is mostly STE products.
    Unless ST is going to play foundry biz, getting Qualcomm to use FD-SOI in next Snapdragon family.

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