The Intel Nanometre

As the world now knows, there’s a nanometre and then there’s an Intel nanometre.

To most of us a nanometre is a nanometre but, to Intel, a nanometre measures 1.182 nanometres.

We know this because the measure of a semiconductor manufacturing process is the drawn gate length.

And, on Intel’s so-called 22nm process, the drawn gate length is 26nm.

Which means an Intel nanometre measures 1.182 nanometres in rest-of -world measurement terms.

That means Intel’s 14nm process, for which it is currently building fabs is, presumably, what the rest of the world would call a 16.55 nanometre process.

Which puts Intel’s 14nm process pretty much on a par with the foundry industry’s 20 nanometre process, and behind TSMC’s 16 nanometre finfet process and Globalfoundries’ 14nm process.

Unless, of course, the ‘Intel nanometre’ has been re-defined and the Intel nanometre now has a new value – maybe the Intel nanometre  now measures 1.25 nanometres? Or even 1.5 nanometres?



  1. Could be this is based on Intel fabs viewed as moving in different inertial frames and the Lorentz contraction.

  2. More on The Intel Nanometre. Following Intel’s last reply to the question: ‘What does 22nm measure in its 22nm process?’ – which I quoted below, I asked Intel two more questions: So 22nm doesn’t relate to anything in particular? and Do you know why that number was chosen?
    The answer I have received to those questions from Intel is: “Quite honestly I don’t know.”

  3. More news on The Intel Nanometre. Asked the question: ‘What it is that 22nm, in the context of Intel’s 22nm finfet process, is a measurement of,’ Intel tell me: “These processes are very complex, and there are many feature sizes. The details we’ve given in terms of fin width, gate pitch and interconnect pitch are all we are willing to share.” Not exactly an answer to the question: ‘What is it that 22nm is measuring? Could it be that nothing measures 22nm on the Intel 22nm finfet IC process?

  4. Yes I’m all agog to hear.

  5. Well that’s what my SRAM numbers showed, but it still doesn’t say what is actually ’22nm’, if anything.

  6. Well I’ve now had a sort of one like ’22nm doubles transistor density from 32nm etc etc etc’, Mike, so I rang Intel and got the answer that all the engineers are off at a conference, they have been asked the question and are pondering the answer and I may get some more insight tonight. As the industry leader Intel’s example matters – and affects behaviour elsewhere,

  7. I suspect you won’t get one. But then I don’t think you would get one from TSMC or GlobalFoundries if you asked them what the node dimension actually means for their forthcoming FinFETs either. 3D changes the rules of the game so much the game needs re-defining 🙂

  8. Thanks very much for this Mike. So far, despite half a dozen messages left on European and American Intel voicemails, there has been no response to my question: “What is 22nm, in the context of the 22nm finfet process, a measurement of.”

  9. Mike Bryant writes:  
    I’ll repeat some useful numbers I’ve given before at our events.  As can be seen for SRAM the Intel 22nm is almost but not quite twice as dense as their 32nm process, whilst TSMC and GF processes fit in roughly to the Intel densities as given by the names of their nodes. 
    Once upon a time half the metal M1 pitch defined the node but in recent years metal pitch reduction has not kept pace with other features so fabs have tended to reference the node as the ratio to the density of SRAM at 65 or 90nm.
    Certainly there is a LOT of market BS taking place as well (Intel included) but in reality Intel does lead the way in density at least.
    Of course SRAM density isn’t everything but with BEOL limited by the desire to stay with single patterning, for logic the metal routing now begins to dominate over transistor size.
    The drawn gate length is not really a relevant measure any more and in any case has never been the official definition of the node. It is generally used to set the performance of the transistor, shorter is faster whilst longer is slower but less leakage.  The move to FinFETs allowed the performance and density of the next node to be achieved without going to shorter gate lengths which would have excessive leakage.
    The additional complication of FD-SOI as a competing process technology will prove interesting.  Despite the hype, FD-SOI SRAM densities won’t match the densest FinFET SRAMs at the same node, but leakage will be noticeably better, causing a definite process branch applicable to numerous applications.
    The stats are :
    (HP and special low power versions are larger for all fabs)
    Intel 45nm SRAM cell – 0.346um^2
    Intel 32nm SRAM cell – 0.171um^2
    Intel 22nm SRAM cell – 0.092um^2
    TSMC 40nm SRAM cell – 0.290um^2
    TSMC 28nm SRAM cell – 0.127um^2
    TSMC 20nm SRAM cell – 0.090um^2
    GF 28nm SRAM cell – 0.120um^2
    ST 28nm FD-SOI SRAM cell – 0.120um^2 (this is believed to be the version with no back-gate and uncompetitive leakage – 0.152um^2 for back-gate and lowest power/leakage but of course LP versions of other processes are also larger)
    Metal pitch
    (once upon a time half this was the node size but as can be seen the transistors have shrunk a lot more than the metal)
    Intel 22nm metal pitch – 64nm
    Intel 14nm metal pitch – 48nm
    TSMC 28nm metal pitch – 64nm
    TSMC 20nm metal pitch – 64nm
    GF 14nm metal pitch – 48nm (predicted)
    Contacted gate pitch
    (this is a key dimension in that it is no point making transistor gates shorter unless you can reduce this number to match)
    Intel 32nm contacted gate pitch – 112nm
    Intel 22nm contacted gate pitch – 90nm (80nm with special processing)
    Intel 14nm contacted gate pitch – unknown
    TSMC 40nm contacted gate pitch – 160nm
    TSMC 28nm contacted gate pitch – 118nm
    TSMC 20nm contacted gate pitch – unknown
    TSMC 14nm contacted gate pitch – unknown
    GF 28nm contacted gate pitch – 113nm
    GF 20nm contacted gate pitch – 80nm
    GF 14nm contacted gate pitch – not relevant as BEOL is stated as being the same as 20nm.  However this may change in due course.
    I hope this helps
     Mike Bryant

    • Hi,

      Could you please give sources for these numbers? I am looking for exactly these numbers but need to cite sources as well.


  10. Ah, metric system, would not a nanometre/nanometer by any other name smell as sweet?

  11. David, you forgot to begin at the beginning: an Intel nanometre is a nanometer

  12. The only way to resolve this, I think, is to ask Intel what 22nm is a meaurement of. This I have done. I will post their reply

  13. David, is TSMCs gate length actually 28nm?
    Answer, no.
    Did you know that GFL’s recently announced 14nm process will have the same gate pitch as its 20mm?
    Node shrinks don’t mean what they used to. But the theme of your article, that Intel’s nodes are inferior to other nodes, is going 180 degrees in the wrong direction.
    Intel 22nm has much higher density as well as lower leakage than 32nm. Its a true node better.

  14. Thanks for that, Dusty, I once heard Andy Grove say: “I get paid to serve Intel’s interest but I don’t get paid enough to lie.” Nowadays Intel’s bosses get paid a lot more than Grove did.

  15. Scott Thompson is chief technologist of startup SuVolta and was running the 90nm program at Intel as a former fellow.
    A panel of experts debated the future of semiconductor technology in IEDM, San Fransico. During the panel, Thompson said as follows:
    “Any time we talk about new nodes, we should wash our mouths out with soap. Intel’s 22-nm node is really 26 nm, so if Intel does new math, so will we.”

  16. Indeed so Keith, only last month Intel presented a ‘7W’ Ivy Bridge processor causing amazement all round because the previous one was 17W – then it turned out that, measured on TDP (Thermal Design Power – the usual metric) the processor was 13W and Intel was using a new metric it had conjured up called ‘Scenario Design Power’. A triumph of marketing until, of course, Intel gets found out and looks silly.

  17. This has been going on for many years. Way back in 1987 I recall that LSI Logic quoted their gate array process channel lengths as effective channel lengths, whereas at Plessey we quoted drawn channel lengths. Of course customers thought the LSI process was better, but in reality it was no different, just better marketing.

  18. I am not alone in thinking this way, Mike, to quote Mojy Chian, senior vice president for design enablement at Globalfoundries: “Intel’s terminology doesn’t typically correlate with the terminology used by the foundry industry. For instance Intel’s 22nm in terms of the back-end metallisation is similar to the foundry industry’s 28nm. The design rules and pitch for Intel’s 22nm are very similar to those for foundries’ 28nm processes.” Spoken at a distinguished gathering – the Future Horizons 2012 IFS in Bratislava.

  19. David – please go away and understand how a process is measured before writing silly articles like this.

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