“We’re extending our tailored approach to the next generation,” said Hu.
“55nm e-flash will be used to create a new family of industrial, smart energy and e-vehicles CPLDs and FPGAs,” said Hu, “it is the result of our 20 year relationship with TSMC. We asked them to develop an optimized process.”
“The 20nm SoC process is the quickest path to a next generation process,” said Hu, “it’s tailored for a broad range of performance and bandwidth-critical applications.”
Hu said that the 20nm process would have 60% lower power compared to 28nm. He added that it had delivered 32Gbps transceivers with total jitter under 9.5 picoseconds.
Hu added that the 14nm finfet process “increases channel performance and reduces power.”
However Hu declined to be drawn on when Altera expected to be in volume production on either the 20nm or the 14nm process.
Of course Altera is using ARM on 20nm planar, will it also use ARM on Intel’s 14nm finfet process – bearing in mind that Intel’s CEO has said Intel will do nothing in its foundry business to enable a competitor?
Hu diplomatically sidestepped that one.
And he followed suit with the tricky corollary: Would Altera put x86 cores in its chips at 14nm?