Asked if Altera is concerned about the fact that its much smaller competitors Achronix and Tabula sre getting wafers from Intel, Bradley Howe, senior vp for R&D at Altera tells me:
“We’re concerned about any competition. Those two companies have fundamental issues and one of them is power. One has a high performance platform and, from what we see, the power is very much higher than the mainstream of the industry can tolerate. They also have issues on the robustness of their design environments. Altera has as many people working on design software as we do on our silicon platform.”
So having your product made on the Intel 22nm finfet process is no guarantee of getting your product into the competitive mainstream. Especially when power is an issue.
Altera itself is moving fast to 20nm, intending to launch 20nm products next year with volume production starting in 2014, says Howe.
The process will deliver twice the density of 28nm and a 60% reduction in static and dynamic power, says Howe. It will deliver 40Gbps transceiver and 28Gbps backplanes. When it is architected for high performance, it will deliver 5TFLOPS DSPs, says Howe.
The 20nm process being developed for Altera’s products is TSMC’s bulk CMOS process. Howe says the TSMC’s 20nm SRAM is now yielding ‘extremely well’ .
In parallel with planar bulk CMOS at TSMC, Altera is “actively working on finfet design right now,” says Howe.
TSMC has said it will be producing a 20nm finfet process and Altera doesn’t rule out using it for a second generation of product.
Altera is also looking at FD-SOI as a possible way to go.