ST To Be A ‘Competitive Follower’ In Process

STMicroelectronics’ strategy of being a ‘competitive follower’ in process technology means that the advantage in gaining access to processing equipment gained by the Intel, Samsung, TSMC lithographic alliance with ASML will not affect ST.

“We intend to be a competitive follower,” says Jean-Marc Chery, Chief Manufacturing and Technology Officer at ST, “we won’t have the first machines. We’ll have them when production is mature.We won’t fight to take machines at the same time as Intel, TSMC and Samsung but we’ll take them when they’re mature. That’s our strategy of being a competitive follower.”

ST gets its basic process technology from IBM’s Common Platform Alliance and, if IBM can’t get the latest production machines early, that will affect IBM’s ability to develop processes in a timely manner for distribution to its alliance partners.

So is IBM being out of the ASML litho party a problem for the Common Platform Alliance? “We have to decide that at the top executive level,” says Chery adding that he would be going to talk to IBM about it quite soon.

The absence of EUV machines doesn’t mean process development has to stop. “Intel have said they can cope with 14nm using double or triple patterning,” says Chery.

As for ST getting its hands on the latest equipment in a timely manner, Chery points out: “ASML capacity is booked 18-24 months in advance. You pay up-front and they will guarantee supply.”

Being left out of the ASML litho party is more of a problem for Globalfoundries, reckons Chery.

ST is making a big bet that FD-SOI technology will deliver wireless chips which are competitive with those made on bulk finfet processes.

“Our 28nm FD-SOI process produces ICs with superior performance to Intel’s bulk 22nm finfet process, said Chery. Intel’s ’22nm’ process has a drawn gate length of 27nm.

“Finfet generation 1 on bulk at 22nm does not perform as well as SOI performance at 28nm,” says Chery, “finfet generation 1 has good leakage without performance, or performance with high leakage.”

“Finfet generation 1 on 22nm is a complex technology and doesn’t give the best trade-off between performance and leakage,” says Chery.

“Finfet generation 2 on 14nm will be the same performance as FD-SOI but much more complex and with less design legacy,” adds Chery.

How will ST compete when the processes deliver the same performance? “Our competitive advantage will be in our design technology,” replies Chery, “Intel is used to making PC chips for high performance, we are in the world of wireless devices where the priority is power consumption.”

ST reckons it has a big lead in FD-SOI particularly in the UTBB [Ultra Thin Body and BOX (buried oxide)] refinement of FD-SOI where the value added is the thickness of the silicon dioxide BOX which is 25nm.

Compared to bulk processes, the FD-SOI process has 10% fewer steps and three fewer masks reducing lead time by 10%. It is scalable to 14nm and has a processing cost equivalent to bulk.

“Planar 28nm UTBB SOI is an evolution of 28nm bulk,” says Chery, “it has the same design rules and the same BEOL process. The FD-SOI FEOL process has 80% in common with 28nm bulk.”

ST is also keeping a foot in the bulk CMOS camp. “We’re prototyping 28nm bulk at Samsung,” says Chery, “we start mass-production on 32nm and 28nm next year.”

“Bulk CMOS is introduced first at Samsung, then at Globalfoundries,” said Chery, “SOI is being introduced first at Globalfoundries where it will be ready for mass production on 28nm FD-SOI in H2 2013. And we can use Samsung for SOI if we need to.”

The Samsung and Globalfoundries fabs are synchronised under the IBM Common Platform Alliance so all the design rules are compatible and the same product fits both fabs.

Part of Chery’s brief at Crolles, as Chief Manufacturing Officer, is to keep the fab there running wafers as cost effectively as anywhere elese in the world.

“The challenge Crolles has in manufacturing technology is to offer a competitive supply chain,” said Chery. ST benchmarks its manufacturing cost against foundry manufacturing cost.

So how does Crolle’s 300mm fab capable of running 14,000 wpm compete on cost with TSMC’s GigaFabs running 100,000 wpm?

“We are competitive in terms of purchasing price,” replies Chery, pointing Crolles is built to make 5000 wafers per week. (it’s running 3,500 wpw at the moment). “At 5K wpw, below 40nm, the advantsges of the dimension of scale is getting lower,” he said, “and full automation means we do not need the high volume to be competitive; with a high level of automation we can manage average volume with strong efficiency.”



  1. is that jingle bells I hear in the air? anyone else?

  2. Engineers praying for that Severance Package as a nice Christmas present I presume?
    As for the corrupt and incompetent Old Boys Gang at Lund’s STE/Sony Mobile, well, they simply weasel onto the gravy reindeer sled that heads for Ericsson this holiday season.

  3. At 5K wpw, below 40nm? Really?

  4. Praying then?

  5. I don’t think there is any italian STE employee either ๐Ÿ˜€

  6. Oh dear. Mario Monti doesn’t look very generous. I can see why ST-E is looking for partners.

  7. Well, after this year’s restructuring round, not that many french employees remain under the STE name, and I’m not sure french politicians want to bail out R&D sites that are located abroad.

  8. M.Hollande perhaps, Djonne?

  9. How could ST survive financially with even more losses from this JV?

  10. Assimilated into ST you mean, STEalthyAnon? Yes, I think this is the likely outcome. When Ericsson get fed up of taking half of ST-E’s debts, Ericsson will hand ST-E over to ST for peanuts. Bit of a game of poker really.

  11. Resistance is futile.
    STE will assimilated.

  12. Yes, Bitter, you are v astute. There’s a bit of a PR effort at the moment.

  13. What they have, though, is a fair bit of Ferro-Fiddling in the Books, we could see a taste of that in the last STE report.
    Anyway, I’ll bet David’s inbox is full of “hopeful” STM/STE emails. Well, as the old proverb goes: “Hope dies last”.
    The cronies will for sure run it to the ground, SOI or not.

  14. SecretEuroPatentAgentMan

    Well, did they *really* spend $2.4 billion on R&D last year or was that the budget? Having worked in R&D myself in various places I can assure you that far from all that goes into this budget is actually spent on R&D. Also when you lump R with D I have seen that there can be hardly any R and the remaining allged D is rather questionable.
    Real R&D gives results, and that is not ST has much to show for.

  15. You’re rather comparing apples and oranges David as Intel and Samsung’s R&D spend is reported somewhat differently to STM’s (or Infineon’s and NXP’s)
    For instance some of the overhead costs at Crolles are counted as R&D as it’s a “lab-fab” and moving more to the R&D line means greater tax credits under the Finance Act 2008.
    Intel can keeps these things separate as US tax law operates differently. Meanwhile Samsung’s accounts are too impenetratable to know what they are reporting ๐Ÿ™‚
    Also you are forgetting that Qualcomm’s R&D spend overtook STM last year and that was pure R&D as they of course have no fabs to fiddle the expenses on.

  16. Too much money devoted to R&D in a too heavily indebted company … seems to me STE is all in with fd-soi and i just think they’re right : fd-soi is certainly double-ace

  17. And the proof of the pudding is in the eating Anonymous, a big R&D spend suggests they’re baking something.

  18. Dont they spend big on st-e as well? And, does it seem to help? The devil is in the details, as someone eloquently put it.

  19. Well Anonymous, ST did spend $2.4 billion on R&D last year which was the third largest R&D spend in the semiconductor industry and behind only Intel and Samsungg

  20. Talk about corporate doublespeak B.S. “Competitive follower” nonsense. Actual meaning: “We neither have the balls nor the minds to stay up front”.

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