The Reason For Intel’s Triangular Fins

The reason why Intel went for triangular fins for its 22nm finfet process has been revealed.

Intel’s triangular finfets suffer a performance disadvantage compared to rectangular finfets says Professor Asen Asenov of GlasgowUniversity who is the CEO of Gold Standard Simulations.

“Intel may have technological reasons for adopting this shape but by doing so you reduce performance by 12-15%,” Asenov told me in July, adding “IBM can make nice rectangular shaped vertical walls.”

IBM is licensing a potentially higher performing design using rectangular finfets to UMC and Globalfoundries and to the other partners in the Common Platform Alliance now also called ISDA (International Semiconductor Development Alliance).

Asked why he thought Intel has adopted this disadvantageous triangular shape, Asenov replied: “We have very little solid knowledge. Maybe there’s a technological reason associated with the deposition of HK gate dielectric over vertical walls.”

Now, EW’s technical editor, Steve Bush, returns from last week’s Imec technology forum with two explanations for Intel’s triangular fins after listening to a presentation by An Steegen, Imec’s senior vice president for process technology.

“Narrow fins get a slope profile to allow STI (shallow trench isolation material)  to fill in the trench,” said Steegen, “another reason to go for slope profiling is uniform implants”



  1. ‘Performance’ is a surprising answer, Anonymous, especially in view of the statement later on in that article that it was thought Intel would return to a rectangular fin at 14nm. Maybe it’s just not Intel corporate policy to concede that the triangular fin was a manufacturing trade-off.

  2. This GlobalFoundry patent claims superior hole mobility with sloped sidewalls.
    Scott Thompson reports from VLSI Symposium that Intel stated that the reason is improved external resistance.
    ” Experts all agree that the ideal FinFETs should have a rectangular fin and yield issues likely drove Intel to alter the fin shape at the end of the technology cycle (potentially a tradeoff resulting from a schedule slip). During the Intel paper Q/A, the presenter (outstanding presentation by Chris Auth) was asked about the fin profile. Many in the audience were surprised that the answer was “performance” (lower external resistance)”

  3. One big challenge in FinFET is to form spacers. You need to clean up the spacer dielectric completely from fin sidewalls, while keeping it on the gate sidewalls. A sloped fin sidewall and tall gate will help.

  4. Pure geometry perhaps – if you can angle your semiconductor structures – at 45 degrees say as opposed to flat, then the die size would shrink proportionally. Not an easy challenge but we’re talking Intel here …

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