Semi Market Annual Growth Rate To Double.

The average annual growth rate of the semiconductor industry is about to double, says IC Insights.

Memory will drive the accelerated growth rate. NAND flash is forecast to grow at a CAGR of 16.6% until 2016, and DRAM is expected to grow 9.6% CAGR till 2016.

The NAND and DRAM growth rates are enough by themselves to double the CAGR for 2011-16 compared to the CAGR for 2006-11.

Especially good news for the industry is that the growth will largely be driven by increasing ASPs.

“The outcome is expected tp be steadily upward-trending ASPsthrough 2016, compared to the 3% annual decline that ASPs averaged between 2006 and 2011,” says IC Insights.

Since Moore’s Law mandates a halving of cost every 18 months, a rising price means high profitability for the semiconductor companies.

Moreover, points out IC Insights, there’s little chance of the spectre of over-capacity spoiling the party.

For this year, the most optimistic forecaster is Semico with a 6-8% growth forecast.

IDC is forecasting 4.6%; IHS expects 4.3%; while Gartner and Future Horizons plump for 4% and IC Insights goes for 3%.

The SIA is forecasting a flat year which, according to Malcolm Penn, CEO of Future Horizons, is “totally and absolutely wrong, it’s not going to be less than 4%.”

It is assumed that SIA forecasts are low because its members want them low to make their own company numbers look better.

Penn expects Q3 to be up 10% which is above the high side of most corporate guidance.

Companies’ own growth forecasts are absurd with such wide spreads that they are meaningless.

Intel is forecasting 2 to 10% growth; Qualcomm -4 to +5%; TI -4 to +4%; ST -5 to +5.5%;  SanDisk 11 to 21%; MediaTek 13 to 18%; Broadcom 1 to  9%; Freescale -7 to +2%; PMC-Sierra at -6 to 0%; Triquint 10 to 15%; Maxim at 0 to  +5%; Altera 2 to 6%.

These forecasts are so wide that their only usefulness is in obscuring what is going on the market.

Last February Intel stopped supplying sales data to the WSTS. Last year AMD left the WSTS.

Without them, and other companies likely to follow estimates of semiconductor market size and estimates of product markets will be guesswork.

Does that matter?

“No one will have any visibility into other peoples’ markets,” replies Penn, “everyone will be flying blind – like they did 20/30 years ago. That’s why they started WSTS in the first place.”



  1. yes. One advantage of having foundries – they publish wafer areas, revenue and profit.
    No way an Intel, STM or other IDM would give away such information.

  2. Are you sure it’s ASP and not processed cost of silicon per unit area, Mike?

  3. What Gordon and Malcolm have both said is that the ASP per unit area has remained the same since the beginning of time. I would qualify this by saying this only applies to mature products – say 40nm and above at the current point in time. It’s also hugely dependent on product mix – MPUs easily go for double that price whilst memories are towards half. Jelly bean parts are lower still. But for SoCs and similar products the $9/sq cm is pretty valid.
    But even though the ASP/area is static, manufacturing costs/area have risen inexorably as a look at TSMC accounts over the years reveals.
    Companies have had to compensate for this by selling more silicon area. Their profit margin per unit area has dropped but if you increase sales it doesn’t really matter. To date the successful ones have done just that.
    I also tend to agree with Ian’s hypothesis and your own response. Our 450mm report for the EC emphasised that 450mm is not just for sub-14nm nodes. However there are large power savings to be had at sub 8nm again as we move into the quantum domain so we will carry on along the curve.

  4. Yes, Keith, I remember the Mostek process guru telling me that scaling would stop at 0.8 micron because that is the wavelength of visible light

  5. I’ve been convinced for a while that scaling will stop at around 10-14nm, at least for silicon CMOS. Maybe it can be done but the cost will mean its no longer worthwhile.
    One’s got to be a bit careful about such predictions though, I have a big tome on my bookshelf with a paper written by a D. Widmann from Siemens in 1977, who predicted that the minimum dimensions for MOS devices was about 0.2um…

  6. I suppose that makes 450mm more compelling but EUV less compelling, Ian

  7. The current predictions are that 20nm will never be any cheaper per gate than 28nm even if you follow the price curves down for several years.
    The same is true for 14nm, maybe there is even a small increase in cost per gate compared to 20nm and 28nm.
    This means the only reason for going beyond 28nm is power saving, and it seems that the predictions for this in real chips may also be optimistic in many cases — basically, operating voltage has almost stopped dropping further, RC time constants are going up, and so power savings are getting smaller and smaller for each new node.
    Or maybe if the die size in 28nm is too big to get reasonable yield, though you need an awful lot of gates for this to be true (or to have most of them doing nothing most of the time like an FPGA) and this normally means well over 100W power consumption.
    So one of the biggest drivers to go to the next process node — lower cost — stops at 28nm. This suggests that an awful lot of designs will stay at this point…

  8. Well I’ve heard both Gordon Moore and Malcolm say that the cost of processed silicon per acre has been unchanged since time began, Mike, but if that is changing then I’ll take your word for it. P.S. Moore put it at $1 billion per acre “a little more for processors and a little less for DRAM,” he said.

  9. Only if the manufacturing cost per unit area stays the same.
    Unfortunately with things like immersion litho, double patterning and everything else being added at each node it most definitely doesn’t stay the same any more.
    In the past the price per cm2 always dropped to a fairly constant value after about two years but since 65nm this time has been extending outwards more and more.

  10. I’m sorry to be so stupid but, if you double the transistors and therefore double the functionality for the same silicon acreage you halve the cost per function. Don’t you?

  11. Moore’s Law only says the number of transistors will double each node with no mention of costs, and the period was throttled back from eighteen months to about two years over a decade ago. Indeed the 90->65nm transition took almost 4 years and we never gained that back.
    One of the most useful data sources are the financial reports of the foundries as they break information down by wafer size and technology.
    Using these one can see that at least for SoCs, neither costs nor probably selling prices have halved at the latest nodes, but if a semiconductor company cannot make a profit with a 4% market growth they really need to get a new management team !

Leave a Reply

Your email address will not be published. Required fields are marked *