Stacked NAND involves stacking transistors on top of each other as in stacked DRAM.
“The debate is about how many hundreds of layers you can stack,” Glen Hawk, vp of NAND Solutions at Micron, told me last year, “nobody knows how many yet. We’re not going to do it until it’s cost-effective – and it needs to be capable of dozens of layers before it’s cost-effective.”
The beauty of stacked NAND is that it removes the need for further scaling. When planar NAND ends, the next generation of NAND – the first generation of 3D vertical NAND – will use a larger geometry process.
The problem which had been looming for NAND’s future viability was that NAND cells have been running out of electrons as they scale down the micron trail. With a few tens of electrons per cell at sub-20nm, NAND behaviour can become unpredictable. Vertical NAND takes that number back up to hundreds of electrons per cell.
The development of stacked, structured, vertical or 3-D NAND – whichever name you like to call it by – has back-burnered the development of alternative non-volatile memory technologies like Resistive RAM, memristors, MRAM etc.
Toshiba doesn’t say how many layers it has stacked but it’s clearly not in its interest to ship stacked NAND until it becomes cost-competitive with planar NAND, and that depends on the number of layers achieved. Micron’s target for marketing stacked NAND is 2015.
In April, Toshiba started on what may be its last planar node for NAND – 15nm.
Samsung has announced it has stacked NAND in production but everyone reckons this was just to get bragging rights and that it hasn’t yet completed development of its final production version of a stacked NAND device.