According to Mentor, 70 per cent of the place and route runtime is in timing analysis and optimisation phases. What Mentor has parallelised is the timing analysis and optimisation phases.
Mentor says its tool can distribute the tasks involved in these phases almost equally across the available cores so that the performance of the tool scales almost linearly with the number of cores.
So, on eight cores, the tool will deliver seven times more performance than one core and on 16 cores it will deliver 13 times the performance.
Although it has only been run, so far, on x86 cores from Intel and AMD the tool can be run on any core.
"It's not tied to any one architecture per se", says Sudhakar Jilla, director of Mentor's place and route group, "we just see cores as something to dump your tasks on." So you could use a SPARC, a MIPS, a Cell, or a PowerPC if you wanted to.
A customer's 150m gate 40nm design took 12 hours instead of three and a half days, according to Jilla, and NEC reported a four times reduction in design closure time on a 30m gate, four mode, four corner IC.
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