“Putting FD-SOI with metal gate last will be an absolutely stunning technology,” says Asenov, “this technology will be the absolute winner and it also solves the problems at 20nm. If the companies which use it play their cards well, they will have a competitive advantage.”
This means finfets will not be needed for a generation or two, while the only company using finfets – Intel – has not seen it deliver any significant advantage in terms of low power.
“In terms of low power, Intel’s 22nm finfet process has no big advantage compared to Intel’s 32nm bulk process,” says Asenov.
There are, of course, advantages derived from the shrink, but little apparent advantage from the fin.
Intel is keeping schtum on the statistical variability of its ’22nm’ (drawn gate length 26nm) process.
“I haven’t seen any data on statistical variability from Intel,” says Asenov, “if they had good variability they would put this at the top of their papers. We have comprehensive data on statistical variability for FD-SOI.”
Key to the value of FD-SOI is the low SRAM supply voltage needed to make SRAMs work.
“If you can develop a metal-gate-last 28nm FD-SOI technology you will be able to achieve an astonishing SRAM supply voltage, in the range of 0.5-0.6V,” says Asenov, “equivalent bulk at 28nm requires approximately 0.9V to secure the reliable operation of large SRAM arrays. Metal-gate-first FD-SOI reduces the minimum SRAM supply voltage (VCCmin) below 0.7V and metal-gate-last FD-SOI at 28nm can reduce VCCmin even further to below 0.5V.”
Asked what is the comparable SRAM supply current for Intel’s ’22nm’ finfet process. “I think it’s 0.8V and may even go down to 0.7V,” replies Asenov.
Earlier this week Jean-Marc Chery, CTO and CMO at STMicroelectronics, said that ST’s metal gate first 28nm FD-SOI process delivered: “An ST-Ericsson NovaThor ModAp platform, with a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V.”