Memory, both volatile and non-volatile, and logic can both be scaled to sub-20nm geometries, according to IMEC and its partners in its core CMOS programme: Intel, Micron, Panasonic, Samsung, TSMC, Sony, Fujitsu, Infineon, Qualcomm, ST Microelectronic and Amkor.
IMEC has developed an implant-free SiGe (silicon germanium) quantum well pFET device featuring a high-mobility SiGe channel with raised SiGe source/drains using bulk-Si substrates.
“This high-electron mobility transistor with an EOT (effective oxide thickness) of 0.85nm achieves a 50% higher saturation drive current compared to Si-controlled pFETs.
The device concept is compatible with additional strain boosters paving the way to deep-submicron scaling achieving high performance,” said the researchers.
For DRAM, IMEC has developed the low-leakage capacitors which will enable the 20nm process node.
To scale DRAM to the 2x nm node, low leakage at an EOT of 0.4nm and less is required, deposited with highly conformal atomic layer deposition (ALD) processes for compatibility with large aspect ratio structures.
IMEC’s record low-leakage MIM capacitors, JG of 10-6 A/cm2 at 0.4nm EOT, enable DRAM scaling to 2xnm.
The capacitors were made on a TiN/RuOx/TiOx/STO/TiN stack fabbed on a 300mm line with DRAM compatible processes.
IMEC has also made progress in resistive RAM – one of the possible replacements for NAND flash.
The operation of RRAM relies on the voltage-controlled resistance change of a MIM capacitor. By finding synergies between conventional logic ICs and RRAM, Imec said it succeeded in setting out the theory for predicting the maximum applicable Vset and revealed that the reset operation corresponds to a pinch off of the filament at its narrowest point.
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