TSMC Developing FD-SOI

TSMC is looking at FD-SOI. That’s not news, but the fact that TSMC has started filing patents on FD-SOI technology is news, and this was reported by Eric Esteve on SemiWiki.

Esteve quotes from a patent filed by TSMC: “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.”

TSMC has had its chances to license FD-SOI from ST and, ever since rival foundry Samsung, took an FD-SOI licence from ST, TSMC must be wondering whether it made the right decision.

As well as FD-SOI’s advantages over bulk, it also has advantages over finfet beyond just lower power. Professor Asen Asenov, Professor of Electrical Engineering at Glasgow University and CEO of statistical analysis specialist Gold Standard Simulations reckons that FD-SOI’s superior scaling characteristics mean that: “14nm FD-SOI will be 40% cheaper than 14nm finfet.”

Moreover, points out Esteve, TSMC’s patent appears to relate to a highly sophisticated mobile IC suggesting that FD-SOI is the best choice in this application.

Clearly all the mobile IC houses are looking at FD-SOI as an option because of its low power potential. The fact that TSMC is developing the technology suggests that a customer or customers have enquired about using FD-SOI,  and TSMC is heavily into bed with near-neigbour MediaTek which is currently motoring.



  1. Thanks Adele. It would be odd if TSMC didn’t pay some attention to FD-SOI. After all it seems better for low power than finfet. Some say FD-SOI won’t scale below 10nm but then some people are saying finfet SRAM doesn’t scale between 22nm and 14nm. And if, as some say, 28nm and 20nm are going to be long-lived nodes then it doesn’t matter so much if FD-SOI doesn’t scale below 10nm. Meanwhile, having an easily migratable route between bulk and FD-SOI (which this patent seems to provide) gives the 28/20nm people an upgrade path.

  2. Mike, I have to agree with David here. Altho there’s some ambiguity in the wording in the middle of the patent (especially when they talk about mapping FDSOI to bulk), this is indeed a patent for an ASIC implemented in FDSOI. BTW, just to be sure I wasn’t missing something, I consulted with some FDSOI experts, and they agree, this is a patent for planar FDSOI (as opposed to FinFETs on SOI, which can also be considered FDSOI, in that they are also fully depleted but FinFETs are of course not “planar” architectures).

  3. Their involvement is taking an FD-SOI design and porting it back to lower cost bulk planar without loss of performance.

  4. These days one feels as God must have done asking Lot to find a righteous man in Sodom, mgp-1, everyone in the semi business has been fibbing for years and no one believes a word anyone says any more.

  5. Why don’t you ask Morris 🙂

  6. Have done so, It says TSMC have filed an FD-SOI patent. I see the patent itself is entitled: ‘Planar compatible FDSOI design architecture’ and the Abstract refers to an ‘ASIC implemented in FDSOI’. Doesn’t that suggest an involvement in FDSOI?

  7. I think you should re-read the article David. It says nothing of the sort.

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