Has SuVolta Got A Good Idea?

The SuVolta approach to reducing leakage looks attractive because it adopts a new approach – looking at levelling up the variations in the threshold voltage of transistors.

An IC has to have enough voltage to make the slowest transistor switch at the same speed as the fastest transistor. Levelling up the threshold voltages reduces the need for the extra voltage required to do this.

SuVolta’s approach takes a different attitude to most people to the leakage problem below 30nm. Most people look for a new type of transistor. SuVolta says it is using bulk CMOS planar transistors. 


SuVolta’s planar transistor can use conventional CMOS manufacturing equipment.


So far, so good. The SuVolta approach looks technologically plausible.


On the other hand you have to ask: Why didn’t Intel license it?


SuVolta is an IP licensing company. Intel has been desperate to find low-power techniques for its mobile ICs.


Intel must have looked at SuVolta’s approach but decided to go with  Finfets, and Finfets are expected to involve a more tricky processing transition than sticking to planar technology.


Other negatives are: SuVolta has been going for six years without attracting a licensee until yesterday’s announcement of a Fujitsu licence; the company has had $48 million of venture money; it has succumbed to dressing up its board with celebrity techies, which is always a bit suspicious; and it’s changed its name – which can imply a loss of credibility in its earlier incarnation.


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  1. Well Intel didn’t invent Finfets but they’re using them, Jamo, and as to the search for ‘satisfactory value’ I think you’re spot on here. Nearly $50 million has gone into SuVolta, and this week’s announcements bear the hallmarks of a campaign to ramp an exit valuation.

  2. @ Robert – NBTI and HCI are both wearout mechanisms. Their paper does mention they compensate for the tranaistor aging so it may be these are what they address. It could also be that the use of lower voltages allows them to reduce the STI stress required as I think this is a very low power rather than high performance process.
    But there is so little detail – and no patent that I can find – that it is hard to judge much at all.

  3. David – Intel would always rather invent than license. So the question perhaps is why not buy SuVolta ?
    I notice that Kleiner Perkins are one of their main investors so they will be using their influence on the ecosystem to ensure SuVolta reaches a satisfactory value, regardless of the real future value.

  4. Suvolta approach seems to conveniently forget about Vt variations due to STI stress and well proximity effects not to mention NBTI and HCI induced offsets.
    Is this a serious paper?

  5. Thank you very much indeed for that, Mike.

  6. http://www.suvolta.com/index.php/download_file/view/44/110/
    explains what they are doing.
    There have been countless papers on doing this since the 90s and NEC (now Renesas) and others already offer a static version of this for ultra low power design. I assume it’s the dynamic approach they they are patenting and they possibly have some form of on-chip circuit that actually measures the transistors and adjusts the bias voltages continually.
    One problem will be routing the two body bias voltages through the cell to each transistor without increasing the cell size or effecting the noise margin of the cell.

  7. Thanks David that’s very good of you. I’d never heard of SuVolta until yesterday so I looked them up and read this stuff about JFETs. Have they told us how they get the effects they describe using bulk CMOS?

  8. David, I asked Scott Thompson, the CTO of Suvolta, if they are pursuing a JFET. here is his reply.
    “DSM started with jfet BUT it has major issues and we moved on to bulk planar CMOS platform 2 years ago. Company even change name to Suvolta when we dropped jfets. Surprisingly, We still get a alot of comments on jfet. People find an old patent and just assume that is what company is still doing.”

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