Current attempts to use multi-cores in the mainstream computing world, like the efforts made by Intel and Microsoft and some US universities, are doomed, according to the Professor of Computer Science at BristolUniversity, Professor David May FRS.
Mentor says that parallel processing accelerates design closure and timing analysis by four times on an eight core machine.
Intel and Microsoft are on a hiding to nothing in their efforts to find an efficient way to programme multi-core processors, according to the Professor of Computer Science at BristolUniversity, Professor David May FRS, who was the architect of the Inmos multi-core processor, the Transputer.
Can using the sea-of-processors approach to address the programmable logic market work? Naturally, John Daane, CEO of programmable logic pioneer Altera, doesn’t think it can.
“The shared memory approach of Intel and AMD to general purpose multi-core processing is like building Hadrian’s Wall with 100 builders spread between Newcastle and Carlisle with one guy with a wheelbarrow delivering the bricks”, says Peter Robertson, managing director of Edinburgh multi-processing company 3L.
It’s been a long time getting out on the market, but at last it’s here. Toshiba announced it’s putting a version of the Cell microprocessor on the market.
If you go onto the Web-site of Montalvo Systems and click the ‘About Us’ button you read: ‘Montalvo Systems is a well funded fabless semiconductor start-up funded by prominent Silicon Valley venture capital firms’.
Interesting to see Intel, for so long the exponent of the big clunking chip, argue that simple cores are better than complex ones.
While Intel codenames its processors, during development, after the names of American rivers, PicoChip of Bath goes one better by calling its processors after the names of Bath pubs.
Xmos, the parallel processing start-up founded by the Professor of Computer Science at Bristol University, David May FRS, who invented the Inmos Transputer multi-core microprocessor, is thought to be targetting the low end of the FPGA market.