SOI Sauce

Although light-hearted, this comment does serve to indicate how new moves to bridge the logic/memory gap could result in breakthrough changes in future system performance. This requirement for change is further exacerbated by the move towards multi-core processors, which require even more memory integration.

Silicon-on-Insulator (SOI) is one of the enablers to bring about these changes.

An example of such an SOI-based memory opportunity is the capacitor-less DRAM, (ISi's Z-RAM). Using the floating body effect, a bit is stored with just one transistor and without additional capacitor, as in a standard DRAM. Another recent example, presented at ISSCC2006 combines a deep trench DRAM capacitor on SOI, suppressing this floating body effect, thereby increasing density and speed, at the expense of retention time, thus cutting power consumption.

Next to increased area density and reduced junction leakage, other specific benefits often attributed to Silicon-on-Insulator memories are the improved immunity to soft error rate and the reduced process variability due to reduced substrate coupling.

These and other benefits will be discussed in the context of factors like cost, wafer supply and design investment, also including the choice between embedded (in System-on-Chip) versus stand-alone (on System-in-Package) memory options, and considering the evolution of these factors in the near future.

On a different note it is worth mentioning that future MEMS solutions for data storage may extensively use SOI substrates for proper patterning of the mechanical read/write elements.

The panel is intended to give further food for thought and to evaluate the appetite for SOI in future memory technologies. If you can't be at ICMTD'07, (http://www.icmtd.com/ICMTD07/07-ICMTD.htm) I'll keep you posted in future Blogs.