Modern communications systems need to handle ever greater data traffic. This is pushing sampling rates of high-speed data converters constantly higher to capture wider signal bandwidths and increasing receiver channels for advanced MIMO antenna configurations.
In order to cope with this the adoption of the JESD204B standard for digital interfaces between high-speed analogue-to-digital converters (ADC), digital-to-analogue converters (DAC) and digital processors is gathering pace across the industry.
JESD204B, an evolution of JESD204, makes it considerably easier to use faster converter sampling rates, simplifies routing, and provides a solution to system synchronisation.
The JESD204B standard addresses a number of challenges not addressed adequately by traditional high speed data converter interfaces based e.g. on low-voltage CMOS (LVCMOS) and low-voltage differential signalling [LVDS] signalling levels. These Include:
• Simplified board routing with much fewer lanes to route. Transitioning a dual 16-bit ADC from a DDR LVDS interface to JESD204B, the output data bus reduces from 34 lanes to as few as six lanes.
• It eliminates the need for data bus line matching for maximum setup and hold times between different data bits and clock on the parallel interface as the clock is now embedded into the serial data stream.
• Using the deterministic latency feature the sampling instance between multiple devices can be aligned independent of bus trace length. Thereby an entire system can be synchronized, enabling large scale data acquisition systems like ultrasound scanners, phased-array radars or wireless base station MIMO receivers.
• Provided each data converter receives the SYNC signal within the same LMFC cycle, aligning the different ADCs is straightforward.
• Device pin count is reduced, enabling the use of much smaller packages for ADCs and DACs and processors/FPGAs, which may bring additional cost savings.
• It is easier to switch data converter resolution since all output data is getting serialized over the same differential pairs.
• The harmonic clocking feature eliminates the need to provide the exact clock to each device in the system. One common reference can be distributed and then integrated clock dividers in individual converter devices will scale the reference to the required sampling clock.
Synchronising multiple receiver antennae
Above benefits can be exploited for example in wireless infrastructure multiple-input and multiple-output (MIMO) radios and other applications such as phased array radars. There multiple receive antennae have been used for many years to improve system performance.
Synchronisation of multiple receivers, however, has proved challenging because the samples must be aligned exactly. To prevent channel-to-channel skew resulting from timing mismatch across different ADCs, timing calibration and precise routing are essential. As converter sample rates and receiver channel count are increasing the challenge gets magnified and transition to the JESD204B interface becomes the logical choice.
New ADCs/DACs equipped with the JESD204B interface are now available. The first such data converter from TI is the dual 16-bit Msample/s ADS42JB69.
TI has designed the ADS42JB69 to address the hardest AC requirements for very wideband signals (e.g. the multi-carrier GSM standard) and it is ideally suited for MIMO receivers. Using one or two lanes per ADC channel, subclasses 0, 1 and 2 are supported with data rates up to 3.125Gbit/s.