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Altera losing the process race with Xilinx

08nov06chipworks.jpgTwo or three years ago, the process technology race between Altera and Xilinx was neck and neck – it was difficult to split the two programmable logic firms. But Xilinx execs will be feeling fairly pleased with themselves this week, as Altera admits it won’t have 65 nanometre samples until Q3 2007. That is staggering, when you consider that Xilinx started shipping 65nm samples, albeit in small doses, in May of this year. When Xilinx launched samples of Virtex-5, the company said its lead on process technology was “Six, maybe nine months.” So why has the process technology gap – which didn’t exist a couple of years ago – grown to more than a year? One reason for this gap is the different approaches of the two companies’ foundries. Xilinx’s foundry UMC worked on a standard process at 65nm – exactly what Xilinx needs. And even if UMC hadn’t come up with the goods Xilinx is also fabbing the devices at second source Toshiba, and could have used its second source fab at IBM. However, Altera’s foundry TSMC has gone for a low power process for its first stab at 65nm – which is not strictly suited to FPGAs. Altera has had to wait for TSMC to get round to doing the necessary higher power process, as it doesn’t have a second source. There’s a good article on the subject of 65nm at Embedded.com – 65nm: Where are the chips? Update: Canadian reverse engineering firm Chipworks has just released a breakdown of the Virtex-5, comparing devices from Toshiba and UMC.

Tags: altera, nine months, programmable logic, reverse engineering, xilinx

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