HP plans new architecture for FPGAs
HP’s announcement that it plans to use its cross-bar technology for a field programmable gate arrays (FPGAs) has been commented on in Cross bar for next generation FPGA by Nick Flaherty.
The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS (complementary metal oxide silicon), using an architecture HP Labs researchers have named “field programmable nanowire interconnect (FPNI)” – a variation on the well-established FPGA technology.
However, so far it’s all modelling simulation – a real life chip doesn’t yet exist. As Nick points out:
One of the challenges will be yield, as the small size of the cross bar on the upper layers will make it sensitive to defects, and that will also hit the cost, so don’t write off traditional CMOS and Xilinx and Altera just yet.