Rooting around in the fascinating stuff at the bottom of a draw labelled 'Engineering - Junk Miscellaneous'. Delving amongst the delightful...
Phase-locked loop triumph
What I like about them is that they servo into the best answer for a given situation – For example, they can get in there and dig a signal out of a whole lot of noise. Arguably, the AFC (automatic frequency control) on an old-fashioned non-synthesised FM receiver is a rather elaborate PLL.
A long time ago, in search of better AM reception – running up a rather blind alley, I admit, as only 3dB noise improvement is possible – I even knocked up a direct conversion receiver inspired by an obsolete app note from Signetics (se below).
This was for one of those NE-series chips that included the NE555 timer. NE56x chips seem to have all been phase-locked loops of some sort and I think it might have been an NE565.
As I remember it, it requires a sluggish loop – unlike FM demodulation with a PLL. The idea was I think, that the PLL (the top loop in fig 1) locks to the incoming signal with essentially a 90°phase shift from the input signal, which puts the 90° arm of the VCO at the correct phase relationship for the bottom mixer to demodulate the AM input into audio.
By using a four-quadrant multiplier for the audio demodulator, both positive and negative parts of the AM envelope are converted to audio, compared with one or the other if a simple diode detector is used, hence the 3dB noise improvement.
As the correct part was no longer available I used the excellent CD4046 CMOS phase-locked loop (see below), and a bunch of CMOS analogue switches for the demodulator.
As it happens, it was never finished because the RF part was fiddly to make, and I had had all my PLL fun once that bit was working – and, after all, AM radios are cheap, they work fine without 3dB improvement, and FM was nicer to listen to anyway.
Such is the folly of youth.
What this did do though, was stand me in good stead when I was a real engineer (I claim) and had to solve an annoying test problem.
A certain test required a frequency that was 100Hz away from an oscillator of a few hundred kHz, buried deep inside a piece of equipment.
The established technique was to measure the oscillator, then adjust a sinewave generator 100Hz away from that frequency.
It was not a crystal oscillator and, as 100Hz is less than 0.1% of the output frequency, thermal drift was an issue. The poor test engineer had to chase it using the knob on the generator, while watching two digital frequency meters, to hold the 100Hz difference long enough to get a clean measurement.
My job was to come up with something that would track 100Hz away from the internal oscillator.
It is a form of ‘offset’ phase-locked loop (see fig 2) and requires a frequency subtractor. If the phases, bandwidths, and polarities are correct, the second mixer allows the loop to lock to the input frequency plus (or minus) the offset frequency. An added feature is that the offset can be changed at will by varying the 100Hz input.
If you are following the circuit, it helps to know it locks with the offset frequency on the output of the subtractor.
The frequency subtractor is normally a mixer plus a low-pass filter. However, and this is the bit I am particularly pleased with, I used a single D-type flip-flop instead of a mixer and filter because, if the frequencies are close enough, a D-type acts as a frequency subtractor. If they are too far apart – greater than 2:1 as I remember – a D-type ceases to be a subtractor, and so could not be used to take 100Hz from 100kHz directly.
The rest of the parts are all available within the CD4046.
As it is has to track just 0.1% away from the input, the circuit is quite demanding. But the nice clean 4046 oscillator coped with no visible jitter, and using its excellent ‘phase comparator II’ for the right hand mixer prevented loop noise – its output is mostly open circuit when the loop is locked, with occasional tiny pulses keeping it locked.
To get it initial lock, there was a circuit around the offset PLL which converted it into a simple PLL. Once locked exactly to Fin, it was switched to the offset configuration and jumped to the offset frequency.
This circuit was follwed by a square to sine converter to make a signal suitable for the test – involving yet another PLL to make a controlled-amplitude triangle wave, and a one FET triangle-to sine-converter (the latter, a very effective little circuit – google it, it has only 1x FET, 2x diodes, 4x resistors).