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Hotspot hot potato

Normally, silicon scaling is a good thing. Except when you are making power devices, as people working in the automotive semiconductor business explained at the Design Automation and Test in Europe (DATE) conference this week in Dresden. Klaus Meder, president of the automotive electronics division at Robert Bosch, explained in…

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MSP430 clones explore limits of MCU power

The Texas Instruments MSP430 is practically synonymous with low-power processors and, although the company may not care much for the idea of clones of the architecture appearing, that is being helped by a crop of research processors that explore the limits of the threshold voltage of CMOS transistors. These…

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Renesas promotes work on power-saving micros

Yoichi Yano, executive vice president of Renesas Electronics made energy saving the theme of his keynote at this week’s International Solid State Circuits Conference, describing some of the techniques the company is putting into action to make silicon suitable for self-powered sensor nodes…

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TI promotes low power at ISSCC

The International Solid State Circuits Conference kicks off next week and Texas Instruments, which unveiled a low-energy digital signal processor last year based on near-threshold logic circuitry, is keen to tout its involvement in more low-power work this year…

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Prototyping's proxy for power

The electronic edition of the winter issue of Chip Design magazine contains a round table discussion about rapid prototyping and the interview wastes no time in asking about the technique’s role in low-power design, which is not quite a direct one yet…

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Clock-speed slowdown continues

It’s no secret that the clock speeds of processors have hit a glass ceiling. But until the latest iteration of the International Technology Roadmap for Semiconductors, we still expected them to increase by close to 10 per cent a year. Not anymore. The slow rise has been replaced by…

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ITRS 2011 published

The 2011 International Technology Roadmap for Semiconductors (ITRS), finalised late last year, has been publicly released. The roadmap looks at the problems facing the chipmaking industry from now until 2026 and includes some updates that focus on low-power design. The slides prepared by Andrew Kahng on design, for example…

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HP Labs pushes for optical interconnect

EETimes has put a video on YouTube that shows short excerpts from the keynote given by HP Labs’ Prith Banerjee at the recent DesignCon in California where he talks about the work being done there to use optical interconnect to take backplane speeds from 10 to 300GB/s and higher…

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