mannerisms

Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.

ASIC Development a Doddle.

ASIC development is a simple business with an 88 per cent likelihood of delivering the chip on time, and a 94 per cent chance of getting it right first time.

All you have to do to match these figures is to stick to a few basic rules, according to Naveed Shirwani, President and CEO of Open-Silicon, whose company is achieving the 88 per cent on-time delivery and 94 percent first time right performances. 1.Select only medium complexity ASICS, say 20m gates on 90nm. “Don’t do 100m gates, few people need it”, says Shirwani. 2. Have a fixed methodology for developing the chips. “Codify the methodology; codify the flow in industry-standard software”, says Shirwani, “a designer at Open-Silicon does not have the liberty to change the tools or change the flow because if a great idea.” 3. Beware of the design manager’s ego. “The design manager’s ego can get bigger and bigger until it’s bigger than the entire company”, says Shirwani, “so don’t do design the same way as everyone else. The team approach is better where the design manager has no headcount, and designers have their own specialised areas, and when a new project comes along, a new team is formed for each project.”. 4. Don’t use risky IP. “We stay 18 months behind the fab, and we stay 18 months behind the IP and we’re proud of it”, says Shirwani, “so let other people try out the IP. We have people validating IP, taking it through a rigorous evaluation process.” 5. Use multiple fabs. “For each chip, optimise the supply chain”, says Shirwani, “what is good for one chip is not good for another. The same is true for packaging and test. One fab, one test, one package can’t be right.” 6. Be visible. “You need to tell people if it’s going to be late as soon as you can”, says Shirwani.

Tags: doddle, fabs, medium complexity, methodology, standard software

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