Programmability Will Save ASIC, Says Daane

How do you overcome the rising costs of ASIC? Add programmability, says John Daane, CEO of programmable logic pioneer Altera.

 

“At 90nm the cost of ASIC development is $30m”, says John Daane, Altera’s CEO, “assuming R&D cost at 20 per cent of the revenues generated, and assuming you gain a 10 per cent market share, that means you have to be addressing a market of $1.5bn. Therefore the justification for ASIC development requires a $1bn+ opportunity.”

 

There aren’t, of course, a lot of $1bn+ market opportunities, and the cost of chip development rises with each generation: $55m at 65nm, $60m at 45nm, $80m at 32nm and $110m at 022nm, so companies have to find ways out of this financial dilemma.

 

One way is to increase your market share and knock others out of the business; another is to add programmability which allows you to address a larger customer base; another is to use older technology; another is to use lower-cost engineers in lower-cost countries.

“But you don’t get production cost decreases or yield improvements on mature processes”, says Daane, “and you get double digit salary increases in Asian but only single digit salary increases in the West while Asian currencies are expected to harden -  the value of the RMB (China’s Yuan basic unit of currency) is expected to double over the next ten years.”

 

The result is that fewer ASICs  are being developed for low to medium volume infrastructure markets, and fewer start-ups are getting funded.

 

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Tags: altera, cost engineers, financial dilemma, generation 3a, market opportunities, programmable logic

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