The Company That Takes ASIC Specs Written On A Napkin

“People don’t believe that there’s an ASIC company that can receive a spec from you written on a napkin and take it all the way to silicon” says  Naveed Sherwani,  CEO of  Open-Silicon, “most companies want RTL or a Net List, but all that our customers need is the money.”

“We have done a chip from a four page description in English by a manager who was not an engineer”, adds Sherwani, “we wrote a technical specification of what he wanted.”

 

Sherwani tells the tale of an acquired company where “everyone left and the purchaser found a chip on the premises but didn’t know what it was.”

 

“We figured out what the chip did,” says Sherwani.

 

“To be able to do that”, he reckons, “you need about 18 different capabilities inside the company and I’ve taken seven years to grow those 18 capabilities.”

 

“The days of one chip with humongous volume are gone”, says Sherwani, “now we have one chip with derivatives. A platform is created, and a bunch of derivatives is made from the platform which have 80-90% of the characteristics of the platform with a small change.”

 

“If we do very low cost we generally do derivatives”, says Sherwani, “give me your platform chip and I can do derivatives at very low cost.”

 

“From the moment the design is finalised we make a prediction about the delivery date plus or minus one week”, says Sherwani, “our success rate is currently 83% and as been as high as 92% because 40nm and 28nm has been unpredictable.”

 

The ASIC industry is holding up well against the competition of FPGAs which have, as a product sector, stopped growing.

 

“There are two to three thousand ASIC starts every year, and 85,000 FPGA starts”, says Sherwani, “but the FPGA business is not going to grow unless they can offer FPGA at ASIC prices. And they can’t do that because FPGA is such an inefficient use of silicon.”

Tags: asic, fpga, premises, seven years, silicon

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4 Comments

  1. Lefty Goldblatt
    June 22, 2011 15:06

    Testing ASICs must be quite a challenge – in order to get 100% coverage on very complex designs?
    A blank FPGA comes fully tested.
    So does “efficient use of silicon” balance against “testing times/coverage/yield” ?
    or is volume still the biggest decider?

  2. Setu Gupta
    June 15, 2010 07:51

    FPGA vs ASIC is a trade-off itself for Power, Flexibility to Reuse Silicon and Money. So FPGA is not gonna die and neither the ASIC would see a magical boom. It’s a pretty stable state of coexistence based on trade-offs.

  3. David Manners
    May 20, 2010 11:35

    If only you could make it as cheap as ASIC, FPGA engineer

  4. FPGA engineer
    May 20, 2010 11:24

    Long live FPGA.

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