A Tale of Two Processes TSMC/Altera, UMC/Xilinx

There’s an eighteen month to two year gap between the adoption of 65nm at Xilinx and Altera. How can the two leading foundries can be so far apart?

Interesting to see how the foundries are still pretty dependent on their fabless customers to get their processes up and running. Take the respective sagas of TSMC with Altera, and UMC with Xilinx. “Altera is our development partner for the G process (TSMC’s name for its high performance process) and they pretty well dictate when a node becomes manufacturable”, says Chuck Byers, Director of Brand Management at TSMC, “because it’s their product needs which drive when a particular process is required at any particular time. We don’t develop a node in a vacuum and then invite the customers in. You can do that at an IDM but not at a foundry.” “TSMC usually ramps the G (high-performance) process first, because that’s the easiest”, adds Byers, “but now with issues like leakage and power management so important, you need your design partners to help you ramp the process node. Our low-power partners went for 65nm first, so that’s what we ramped first.” TSMC has 15 customers for its low-power 65bn process, all of which operate in the wireless and consumer sectors. It shipped 7,000 300mm 65nm wafers last year. Altera is now saying it will be using the TSMC high-performance process in 2008. By contrast, Altera’s main rival, Xilinx has been shipping product made on UMC’s high performance 65nm process since March 2006. “We work very closely with the equipment people. We’re unusual, in that respect, for a fabless semiconductor company”, says Wim Roelandts, CEO of Xilinx, “we help our foundries, Toshiba and UMC to bring their 65nm process to market. That’s why they can do it and TSMC can’t.”

Tags: altera, power partners, sagas, wim roelandts, xilinx

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