mannerisms

Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.

Another Nail In The ASIC Coffin

Another nail in the coffin of ASICs?  Xilinx’s 20m ASIC gate stacked silicon FPGA will accelerate the process of replacing ASICs, says the company’s CEO Moshe Gavrielov.

 ”In a few years, it’s just going to be ASSPs and FPGAs,” he says, “ASICs are going to disappear.”

“The barriers to doing ASICs, technically and financially, are becoming almost insurmountable,” he says, “by definition, if they don’t hit first time they miss half the market and, if they miss twice, they miss all the market.”

“The ASIC world used to be subsidised heavily by Japanese IDMs,” says Gavrielov, “as they depart and give up their own manufacturing and go to TSMC, you don’t get any advantage in going to a Japanese ASIC manufacturer. ST are still there but I think it’s a very painful business for them.”
 
The company’s 20m ASIC gate FPGA uses 2.5D stacking to put four FPGA die aligned side by side on a silicon interposer. The interposer includes over 10,000 high speed interconnects between each die.

Asked why the ASIC vendors couldn’t follow suit with a 2.5D stacked silicon approach of their own, Gavrielov, replies: “We think we have the right architecture and the tool flow to support it. We provide the tools that enable it, and that’s a big deal. If you have to go out and beg for the tools, that’s not attractive.”

Tags: asics, gate fpga, high speed, moshe gavrielov, xilinx

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9 Comments

  1. Lefty Goldblatt
    November 03, 2011 12:23

    we need to get a new cheap-and-cheerful (chinese?) vendor in FPGA space.
    a simple (long out of patent) approach will do fine – LUT4′s and implemented on a bleeding edge node.
    FPGAs arrive fully 100% tested – so they are good to go without testability coverage headaches,etc.

  2. Ian Dedic
    November 02, 2011 17:49

    @Keith : Tabula do claim much smaller area and lower cost, but if you read very carefully they don’t claim any power saving compared to conventional FPGAs — fewer gates time-shared and clocked faster save a lot of area but not power (their own figures show this).
    This could mean the same processing power as Xilinx’s stitched FPGA but on a single die and presumably a lot cheaper (also avoiding the silicon interposer).
    So it helps solve the big FPGA cost problem (if you need to ask how much the Xilinx chip costs you probably can’t afford it) but not the power problem…
    Of course if you can’t afford the tens of millions of dollars and more than a year to design a high-end ASIC this won’t help either ;-)

  3. Mike Bryant
    November 02, 2011 10:12

    @Eric : I wasn’t thinking of a programmable array so much as a whole raft of analog system blocks which would meet most applications in much the same way as SERDES now performs a lot of high speed digital interfacing. Pin count on modern devices allow this.
    @Ken : I totally agree. There are some excellent general purpose ARM based SoCs now appearing. Motorola/Freescale introduced this concept 2 decades ago of course but everyone else now seems to be catching up.

  4. Keith
    November 02, 2011 08:53

    Instead of stacking die physically, why not do it in the time domain… much cleverer, cheaper, and lower power: http:\\www.tabula.com

  5. Ian Dedic
    November 01, 2011 15:17

    You can indeed use 5 “20M gate” FPGAs instead of a 100M gate ASIC so long as you can put up with the resulting 500W or so power consumption and $10000 or so cost…
    And saying that power will drop with more advanced processes just ignores the fact that system complexity grows even faster, because people design systems to use what can be designed and manufactured.
    Of course for small volumes or where power and cost are less important than time to market FPGAs will win out. If you can produce a usable solution in FPGAs then it’s probably the right one, but in many cases they just take too much silicon and power. If you need a low cost low power solution and you need it quick, there probably isn’t one :-(
    The simple reason that ASIC vendors don’t use this 2.5D approach is that they don’t need to, their silicon area is about 10x smaller so they can get it all onto one chip anyway ;-)
    Horses for courses, as usual…

  6. Eric Janson
    November 01, 2011 13:32

    The old idea of a programmable array of analog bits has been tried many times, and failed as many. Just have a look at how many different data converters and other signal chain building blocks there are. Trying to get the right ones on a programmable array narrows the useful application field far too much for the thing to be affordable. There is a reason there are literally hundreds of different Op Apms, and scores of different data converters available – and more and more as time goes on.

  7. Ken
    November 01, 2011 13:03

    I think the LPC will knock a lot of FPGA’s out. We have an FPGA design, taken 1000′s of man hours to get this far, 12 layer PCB, complex and expensive dev tools, whereas an LPC1768 is about £8 ea in single quantities, you can use 2 layer board, dev tools are easily available, and to make it do things is easy. If you want CAN on an FPGA, thanks thats an extra £4000 license fee, its built in to the LPC. Also USB, I2C, RS232/485, PWM etc etc. And I just saw the LPC1100 series are down to $0.49 ea. There are a few applications where an FPGA is handy, but ……

  8. Mike Bryant
    November 01, 2011 10:21

    A while back when Analog Devices was more a DSP company they might have been losing a bit more sleep. I think what will cause them worries is when Xilinx replace one of those die with one full of high performance analog bits like convertors.

  9. greg
    October 31, 2011 17:31

    Its all about price per part in volume. On the analog asic side…I don’t think the heads of analog devices or linear tech are losing sleep just yet.