Seconds Out For The Next Round Of The Programmable Rumble

Although they are friends, the CEOs of Altera and Xilinx preside over one of the keenest rivalries in the semiconductor industry.

Founded within a year of eachother in 1983/4, their respective fortunes have waxed and waned over the years. When one comes up the other goes down.

 

In the early ’90s, Xilinx held a substantial lead but Altera started to claw that back and, by ’97, had taken a narrow lead at $631 million revenues  to Xilinx’s $568 million.

 

Altera reigned until 2001 when Xilinx stormed back with revenues twice as large as Altera’s.

 

Since then, Xilinx has held onto the lead but, last year, the gap narrowed significantly. Altera had $1.9 billion in revenue; Xilinx had $2.3 billion.

 

This year, Altera expects to be only 3 points of market share behind, says CEO John Daane

“Analysts expectations are that we’ll come in with $2.2bn of revenues this year and Xilinx will come in at $2.35bn,” Daane tells me.

What has helped Altera to close the gap is success at the 40nm node.

“At 40nm we have two thirds – 67% – of the market,” says Daane, “we will be No.1 in the market in the next couple of years.”

Whe I put this to Xilinx’s CEO, Moshe Gavrielov, he responds:  “They have been gaining market share because we slipped on 65nm with no high volume product and, on 40nm, they were out with product ahead of us, but we have the best product with the most applications on 28nm, so the market share situation will swing back to us. We were definitely the first to tape out on 28nm. We’ve taped out six devices. We’re supplying customers broadly. We’ve sold thousands of 28nm devices to over 50 customers. At the end of our financial year in March 2012 we’ll have shipped several tens of millions of dollars worth.”

Daane says Altera had $2 million worth of sales on 28nm in Q3 2011.

So the 25 year-long struggle between the two companies will depend, for the first part of this decade, on their execution at 28nm.

And with Xilinx, a long-time UMC customer, moving to TSMC for the 28nm node, both will be using the same foundry. But not the same process.

“They went with HP and LP (TSMC’s high power and low power processes). We worked on developing HPL, a derivation of HP with the same performance but lower power. It will broaden our applicability in the market,” says Gavrielov.

This is going to be interesting.

Tags: john daane, node, semiconductor industry

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6 Comments

  1. David Manners
    November 29, 2011 12:52

    Ah, Yes, I see, Mike, it’s not just A’s or X’s fortunes (or even L’s) that are at stake when a new generation of FPGA comes out but the fortunes of A’s, X’s and L’s customers. That’s high stakes indeed.

  2. Mike Bryant
    November 29, 2011 12:39

    Because A’s customers sometimes beat X’s customers to market, and sometimes they don’t.
    Even if you are locked into A or X (or heaven preserve you L), it isn’t the FPGA that will make you succeed, it’s just an enabling technology for your clever application.

  3. David Manners
    November 29, 2011 12:03

    So how come the market share figures are quite volatile, Lefty?

  4. Lefty Goldblatt
    November 29, 2011 11:38

    Mike’s point is spot on. Vendor lock-in is eventually what occurs, the specific libraries and soft/hard IP blocks – and familiarity with the design tools.
    Perhaps there is an opportunity for a migration/evacuation kit to provide compatible libraries and steal some seats from each other.

  5. Mike Bryant
    November 23, 2011 20:33

    I suspect inertia will be the main factor. At the VHDL level on pure array of gates migration between the two is possible but as higher level features are added in hardware and software migration will become very difficult.

  6. RobertI
    November 23, 2011 15:26

    I don’t think that the technology node is going to remain as the most important differentiating factor. Rather, the design tools will (IMHO) become more important. Currently all FPGA/CPLD vendors are trying to make the design task easier/quicker, adding support for system-level tools like Simulink and languages other than VHDL and Verilog. Whoever gets that ‘right’ first (for an as-yet-unknown definition of what is ‘right’) will probably get a lot of customers switching from its competitiors.
    In the meantime, my VHDL-fu is good.

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