FD-SOI Can Deliver Leading-Edge European IC Process Technology

Next month customers can start prototyping on STMicroelectronics’ 28nm FD-SOI process which delivers 30% better performance than 28nm bulk CMOS, according to ST’s CTO and CMO Jean-Marc Chery.

From there the planned progress down the micron trail to 14nm is dramatic: another 30% improvement at the same operating voltage at 14nm; a 50% reduction in power at the same speed at 14nm; and a 40% reduction in die area at 14nm.

The figures can be further improved by biassing. Forward body bias on 14nm FD-SOI gives another 15% performance at the same operating voltage; reverse body bias reduces power by another 10% while maintaining the same speed.

These are the advantages which may have persuaded the EC and 19 partner organisations in seven European countries to stump up $360m million over three years to get FD-SOI up and running in ST’s Crolles fab and Globalfoundries’ Dresden fab.

Under this programme called ‘Places2Be’, Dresden will be the volume production fab, but Crolles still intends to run a significant number of FD-SOI wafers – under 2000 wafers a month now, but hitting 8000 wpm in the 2016/7 timeframe when the intention is to start introducing 10nm FD-SOI.

For the moment, the aim is to get 14nm FD-SOI ready for customer protoyping in Q2 2014. The 14nm PDK is done, 14nm IP will be ready this year, 14nm test vehicles are planned to qualify the process by year’s end.

“We must be ready with 14nm FD-SOI before anyone has Finfet at 14nm,” says Chery. Finfet is a complex, more expensive process, and Chery is banking on customers wanting a low-cost, simpler process for consumer electronics applications.

If FD-SOI will take him all the way to 7nm, Chery will be happy, but if  Finfet on SOI is needed at 7nm then so be it. The IBM alliance is developing that process.

Chery says he can do all the R&D, including IP and process development, for $300 million a year. With Places2Be he gets another $120 million a year to spend, and a host of partners.

He’s just negotiated better terms under the IBM development deal, and is willing to talk to anyone who wants to license the technology in exchange for wafers.

Next year a $3 billion, growing, consumer IC business at ST will support further FD-SOI development.

FD-SOI is beginning to look like the best boost for European process technology since the Siemens-Philips MegaProject in the mid-1980s. The MegaProject, and its successor Jessi, restored Europe’s position at the leading edge of process technology, driving Siemens, Philips and ST into the world top ten semiconductor league.

FD-SOI could get the European show on the road again.

Tags: jean marc, volume production

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2 Comments

  1. david manners
    May 23, 2013 20:21

    Yes Ian, ST working with Imec is a very promising step and today’s announcement by Neelie Kroes of a plan to get Europe back to a 20% share of the world chip market is a revelation. Kroes is a star to have got this lot together. And, as you say, FD-SOI may rival finfet. A bright new dawn for the European semiconductor industry.

  2. Ian Dedic
    May 23, 2013 17:00

    And Places2Be wins the 2013 “Most Contrived Acronym” award for…

    “Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe”

    Still, it’s a very promosing rival to FinFET at 14nm with several advantages for minimising power consumption (lower capacitance, lower variation, back biasing).

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