Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.
Full Interview: Jean-Marc Chery, CTO and CMO at ST.
In the last couple of weeks there have been two posts extracted from an interview with Jean-Marc Chery, Chief Technology Officer and Chief Manufacturing Officer of ST Microelectronics. This is the full interview:
In the first week of September STMicroelectronics taped out the 28nm FD-SOI NovaThor integrated modem and applications processor designed by ST-Ericsson.
The chips are being made at Crolles. The Crolles 28nm FD-SOI line has capacity for 300-500 wafers per week. The process is in the course of being transferred to Globalfoundries’ Dresden fab where it will be ready for mass production in the second half of 2013, said Chery.
The decision to go with FD-SOI was taken in July 2011 after an earlier decision to use bulk
“28nm bulk with HKMG looked good enough to address smartphones,” said Chery, , “over a year ago we taped out HKMG 28nm at Samsung.”
Having made the decision to adopt FD-SOI last July, it has taken a year to get the process to the point where it will be ready to start running 28nm FD-SOI ICs next week.
The 28nm FD-SOI process produces ICs with superior performance to Intel’s bulk 22nm finfet process, said Chery. Intel’s ’22nm’ process has a drawn gate length of 27nm.
“Finfet generation 1 on bulk does not perform as well as SOI performance at 28nm,” said Chery, “finfet generation 1 has good leakage without performance or performance with high leakage.”
“Finfet generation 1 on 22nm is a complex technology and doesn’t give the best trade-off between performance and leakage,” said Chery.
“Finfet generation 2 on 14nm will be the same performance as FD-SOI but much more complex and with less design legacy,” added Chery.
How will ST compete when the processes deliver the same performance? “Our competitive advantage will be in our design technology,” replied Chery, “they’re used to making PC chips for high performance, we are in the world of wireless devices where the priority is power consumption. They’re OK with small volume high value PC chips, not with the very high volumes of tablets and phones where volumes are very high and prices are
ST reckons it has a big lead in FD-SOI particularly in the UTBB [Ultra Thin Body and BOX (buried oxide)] refinement of FD-SOI where the value added is the thickness of the silicon dioxide BOX which is 25nm.
Compared to bulk processes, the FD-SOI process has 10% fewer steps and three fewer masks reducing lead time by 10%. It is scalable to 14nm and has a processing cost equivalent to bulk.
“Planar 28nm UTBB SOI is an evolution of 28nm bulk,” said Chery, “it has the same design rules and the same BEOL process. The FD-SOI FEOL process has 80% in common with 28nm bulk.”
ST is keeping a foot in the bulk CMOS camp. “We’re prototyping 28nm bulk at Samsung,” said Chery, “we start mass-production on 32nm and 28nm next year.”
“Bulk CMOS is introduced first at Samsung, then at Globalfoundries,” said Chery, “SOI is being introduced first at Globalfoundries where it will be ready for mass production on 28nm FD-SOI in H2 2013. And we can use Samsung for SOI if we need to.”
The Samsung and Globalfoundries fabs are synchronised under the IBM Common Platform Alliance so all the design rules are compatible and the same product fits both fabs.
The FD-SOI process will see ST through the 28nm and 20nm nodes without ST having to bother with finfets.
“At 28nm and 20nm we can offer a planar SOI solution which offers the best combination of performance and leakage,” said Chery
The FD-SOI vs finfet competitive battle will be joined in earnest at the 14nm node, reckons Chery.
“Intel’s 14nm finfet process will be fantastic,” said Chery, “so Samsung and TSMC are running fast to introduce a competitive 14nm finfet process.”
ST’s FD-SOI process will scale to 14nm but, after that, ST is looking for partners to develop the technology further.
“The challenge for us will be at 10nm,” said Chery, “because bulk will disappear at 10nm. We need to get others to join the club at Globalfoundries – it’s in our interest to prepare a club for 10nm.”
Chery reckons the FPGA people and the ARM camp could be possible members.
STMicroelectronics’ strategy of being a ‘competitive follower’ means that the advantage in process technology being gained by the ASML, Intel, Samsung, TSMC lithographic alliance will not affect ST.
“We intend to be a competitive follower,” says Jean-Marc Chery, Chief Manufacturing and Technology Officer at ST, “we won’t have the first machines. We’ll have them when production is mature.We won’t fight to take machines at the same time as Intel, TSMC and Samsung but we’ll take them when they’re mature. That’s our strategy of being a competitive follower.”
ST gets its basic process technology from IBM’s Common Platform Alliance and, if IBM can’t get the latest production machines early, that will affect IBM’s ability to develop processes in a timely manner for distribution to its alliance partners.
So is IBM being out of the ASML litho party a problem for the Common Platform Alliance? “We have to decide that at the top executive level,” said Chery adding that he would be going to talk to IBM about it quite soon.
The absence of EUV machines doesn’t mean process development has to stop. “Intel have said they can cope with 14nm using double or triple patterning,” said Chery.
As for ST getting its hands on the latest equipment in a timely manner, Chery points out: “ASML capacity is booked 18-24 months in advance. You pay up-front and they will guarantee supply.”
Being left out of the ASML litho party is more of a problem for Globalfoundries, reckons Chery.
Part of Chery’s brief at Crolles, as Chief Manufacturing Officer, is to keep the fab there running wafers as cost effectively as anywhere else in the world.
“The challenge Crolles has in manufacturing technology is to offer a competitive supply chain,” said Chery. ST benchmarks its manufacturing cost against foundry manufacturing cost.
So how does Crolle’s 300mm fab capable of running 14,000 wpm at the moment compete on cost with TSMC’s GigaFabs running 100,000 wpm?
“We are competitive in terms of purchasing price,” replied Chery, pointing Crolles is built to make 5000 wafers per week. (it’s running 3,500 wpw at the moment). “At 5K wpw, below 40nm, the advantages of the dimension of scale is getting lower,” he said, “and full automation means we do not need the high volume to be competitive; with a high level of automation we can manage average volume with strong efficiency.”
Crolles currently produces 22% of ST’s annual sales – about $2 billion worth. “The number of good circuits per wafer is between 70% and 90% depending on complexity and ramp up. The challenge is always how to align the wafer cost to TSMC’s selling price.”
The manufacturing strategy varies with the industry cycle. In a down-cycle the strategy is to have 60% out output manufactured in-house and 40% out of house; in the up-cycle the proportions are reversed: 60% out at foundry and 40% in-house.
ST uses the Fast-Yield Learning Curve technology of PDF Solutions.which has brought days-per-mask-level down to 0.7. “With one customer’s apps processor on 40nm we have achieved 0.36 days per mask level,” said Chery.
ST will pursue two options at 14nm. “We don’t want to be a follower of Intel,” said Chery, “at 14nm we’ll have both options: 14nm finfet in bulk – from the Common Platform Alliance, and 14nm FD-SOI planar.”Tags: chery, chief technology officer, design technology, dresden fab, wafers