Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.
So what’s happening with 28nm?
Nvidia, which pays for its chips by the wafer, has blamed low yields on 28nm for a decline in profit margins.
“The gross margin decline is contributed almost entirely to the yields of 28nm being lower than expected,” says Nvidia CEO Jen-Hsun Huang.
Because Nvidia has a wafer-based pricing arrangement with TSMC, the fewer die per wafer then, obviously, the higher the die cost.
Last month at IFS2012, Mike Bryant, CTO of Future Horizons, said that several customers were experiencing yield problems on TSMC’s 28nm process.
All that TSMC would say in reply was that the 28nm ramp was 3x faster, and defect density issues 3x better, than the 40nm ramp at the same stage. However 40nm was a notoriously tricky node.
Xilinx recently said it is having the fastest new-node product roll-out in its history having shipped four of its five 28nm product families in 11 months. That is half the time it took to roll out initial devices in two product families at 40nm.
Nvidia, of course, makes very large die which are more likely to have defect densities, which could account for the different experiences of Xilinx and Nvidia.
Also Xilinx uses the HPL version of TSMC’s 28nm process while Nvidia is using the HP version.
Not many can do 28nm. Intel – with its 32nm equivalent obviously – and Samsung up to a point, are the only ones. GloFo is said to measuring its 28nm yield in wafers-per-die. ST-Ericsson has still not announced its 28nm fab.
It all goes to show how difficult advanced nodes have become, how crucial they remain to competitiveness and how ineffably silly it was of the financial community to press their view that advanced CMOS manufacturing was a commodity.Tags: gross margin, Nvidia, tsmc, wafer, wafers