Intel Delays Finfets.
“Intel was supposed to have 22nm at the end of this year or Q1 2012. Now this has been moved forward to sometime in 2012,” says Professor Asen Asenov of GlasgowUniversity and Gold Standard Simulations (GSS).
“Everyone is very curious that there is no IEDM paper from Intel about Intel using 22nm finfets,” Asenov tells me.
Usually if Intel is introducing a new technology in the year ahead, they have a paper on it at IEDM but, although Intel has a paper on compound finfets made on an InGaAs process at this week’s IEDM, it does not have a paper on 22nm finfets made on a conventional CMOS process which Intel says will be the process used for its 22nm finfet production.
“Intel announced in May that it would use finfets at 22nm,” says Asenov, “the hidden agenda behind this was because Intel was unable to scale its SRAM cell from 32nm to 22nm using bulk Mosfets. That’s why they were forced to introduce finfets.”
Although the finfets to be introduced by Intel are to be built on a conventional CMOS silicon substrate, Asenov’s group at GlasgowUniversity has determined that SOI finfets may be easier to make.
“Intel has chosen bulk because it is the cheaper option, but it has a lot of problems in terms of manufacturability and control,” says Asenov.
Asenov reckons that finfets built on an SOI substrate could have significant advantages in terms of simpler processing, better process control and reduced statistical variability.
His group has shown that SOI finfets will meet the low statistical variability requirements of 11nm CMOS technology.
That means SOI finfets will be useful for three generations of process technology justifying the expense that will be incurred in moving to new transistor architecture.
“When you introduce a new device architecture you hope this will allow you to scale for several process generations – if it looks like it will only scale for one generation, it is not a good investment,” says Asenov, “we have shown we can scale SOI finfet for three generations – 22nm, 16nm and 11nm.”
Asked if there was any difference between what Intel calls a ‘trigate’ transistor and what the rest of the world calls a finfet transistor, Asenov replies: “Not a lot really. Trigate is a specific implementation of finfets. They use the word trigate as a differentiator.”
Asked if there were significant differences between finfet transistors and fully depleted SOI transistors – the two main contenders to be the next mainstream IC transistor, Asenov replies: “Fully depleted SOI has very similar advantages to finfets.”