Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.
NAND process geometries have become as problematic as logic process geometries with the advantages of further scaling – especially as 3D NAND approaches – being questioned.
NAND process geometry is currently at 20nm and should be 10-20nm in 2017, says IC Insights adding “reported minimum feature sizes and mass production definitions are very imprecise and may be influenced by marketing numbers games.”
Samsung, Hynix, Toshiba, and IM Flash are currently bringing up volumes of NAND with 15-16nm minimum feature sizes.
SanDisk says that 19nm will be its NAND process for two generations – with the second 19nm generation using a reduced size memory cell on the same process geometry. SanDisk/Toshiba have already started producing on the first of these 19nm processes.
IM Flash believes 2D NAND flash technology can be scaled to 10nm and that 3D NAND would take over from there. The company also said that 3D NAND would have to be manufactured with at least 32 layers to be economically feasible.
In May, Samsung started volume production of its V-NAND flash chips using 32 memory cell layers. The company had previously shipped a limited number of solid-state drives (SSDs) based on its first generation 24-layer V-NAND technology to some of its data centre customers in 2013.
Other NAND flash manufacturers are hoping to begin production of 3D NAND parts in 2014, but 2015 appears more likely. Micron has said that the feature sizes of its first generation 3D NAND may be larger than those of the last generation of 2D NAND.
So as long as life remains in 2D devices, 3D technology will not be rushed into the marketplace. The timing of a full-scale transition from 2D to 3D NAND memory depends on when 3D becomes a cost-effective option to 2D, and that situation is still a ways off, says IC Insights.
And even when the cost crossover point is reached, 2D and 3D NAND will likely coexist for several years.