The Future Of Process Is Wide Open
The options for the future of process technology are still wide open with three choices: finfet on bulk, finfet on SOI and planar FD-SOI, says Asen Asenov, Professor of Electronics and Electrical Engineering at Glasgow University and CEO of Gold Standard Simulations, the leading CMOS statistical variability company.
“It’s a battle between Intel and IBM – between SOI finfet and bulk finfet,” Asenov told EW, “while ST’s FD-SOI offers a very good low power solution. FD-SOI in terms of simplicity has advantages.”
Recently Asenov gave an invited paper at DAC on the process implications.
“The main problem with FD-SOI is that there’s not enough infrastructure. In terms of ecosystem there’s not enough people,” adds Asenov, “everyone is focussing on finfets because that is what Intel is doing. I think FD-SOI is a very good technical solution. You can reduce the power by back-biasing – finfet is insensitive to back-biasing – but FD-SOI has very good back-bias sensitivity.”
FD-SOI depends on STMicroelectronics for its development. ST is running 28nm FD-SOI wafers at Crolles in quantities under 2k wpm but it has transferred the process to Globalfoundries’ fab in Dresden. ST is also looking to license the technology to widen the FD-SOI ecosystem.
“ST’s is in a very good position, it has very good relationships with SOITEC and LETI,” says Asenov, “the French government is pumping money in.”
Under the $100 billion Places2Be programme announced by EU vice president Neelie Kroes last month, the EU is putting up €360 million to support FD-SOI manufacturing in Dresden and Crolles. Half of ST’s R&D budget – some $300 million – will also be going to support the FD-SOI development.
This is vital for the future of Europe as an economic entity, reckons Asenov : “If we are without an advanced semiconductor industry we will become a third world country,” he says, “it’s very important for Europe to wake up and realise that semiconductor technology is the technology behind all these digital applications.”
As for the IBM-Intel contest between finfet on bulk and finfet on SOI, Asenov points out that this is another ecosystem battle. Bulk has a big ecosystem; SOI’s is much smaller.
Clearly finfet on bulk has disadvantages because Intel has given up on having the ideal rectangular shape for its fin, going for a trapezoidal fin which diminishes the performance of ICs made on the process by 15%.
Intel hasn’t said why it went for the trapezoidal shape but Asenov has some ideas:.
“In bulk finfet you need to etch the fin,” says Asenov, “to provide the insulation you need to etch the fin and then carry on digging a trench into the silicon which is two to three times deeper than the height of the fin. Also depositing high K oxide may be easier with a trapezoidal fin.”
“Compared to a rectangular fin, Intel’s trapezoidal fin delivers 15% less performance for the equivalent height and width,” says Asenov.
However, IBM, by using SOI finfet, has shown it can get closer to the ideal rectangular shape.
“IBM has shown they can get a better shape,” says Asenov, “there’s some rounding of the top of the fin – because with the perfect rectangular shape you sometimes get high electrical fields which may produce reliability problems.”
So why doesn’t Intel go for SOI? “Intel went for this more complicated technology because it’s afraid of being dependent on a single supplier of SOI wafers – SOITEC,” replies Asenov, “and Intel’s s also worried about the volume of wafers it could get from SOITEC. “
“Soitec understands Intel’s problem and has licensed it to other companies, and so the supply of SOI is better,” says Asenov.
Apart from Globalfoundries, the foundries haven’t gone for SOI either. Asked why not, Asenov replies: “Making SOI finfets is cheaper than bulk finfets, but SOI wafers are more expensive, so if a foundry goes to SOI it has to give some of its profits to the SOI manufacturer. So bulk is better for foundries and that’s why they’re going for bulk at 16nm and 14nmm. But SOI has the advantage. For foundries it’s not the most important thing to have the best technical solution but to have the solution which produces the most revenue.”
So the battle for the future of process stacks up: bulk finfet vs. SOI finfet vs. FD-SOI.
FD-SOI is the wild card here because it is a European solution, while America is going for finfet.
However FD-SOI scales well. 28nm FD-SOI delivers 30% better performance than 28nm bulk, says ST’s CTO and CMO Jean-Marc Chery, 14nm delivers another 30% improvement in performance at the same operating voltage, a 50% reduction in power at the same speed, and a 40% reduction in die area.
This can be improved by biassing. Forward body bias on 14nm FD-SOI gives another 15% performance at the same operating voltage; reverse body bias reduces power by another 10% while maintaining the same speed. Biasing is not an option for finfet.
For the moment, the aim is to get 14nm FD-SOI ready for customer prototyping in Q2 2014.
The 14nm PDK is done, 14nm IP will be ready this year, 14nm test vehicles are planned to qualify the process by year’s end.
“We must be ready with 14nm FD-SOI before anyone has finfet at 14nm,” says Chery.
Chery expects that finfet’s complexity and expense will put off consumer customers wanting a low-cost, simpler process.
Tags: french government, power solution, stmicroelectronics, technical solution, variability