mannerisms

Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.

The Honest Process Guy

Honesty about process technology is as rare as hens’ teeth these days, so ST’s CTO appeared as a refreshing incarnation of truth at ST’s investor day in London yesterday.Talking about ST’s 28nm and 14nm second source deal with Globalfoundries, Jean-Marc Chery, ST’s CTO, said: “Today what people call 14nm is actually 20nm – it’s the same for everyone.”

For instance, everyone knows that Intel’s 22nm process is actually 26nm – taken from the measure of the gate length.

Similarly ST’s 28nm FD-SOI process is actually a 24nm process measured by gate length.

A 2nm difference in gate length shows Intel’s much-vaunted process lead is not so big as it might appear.

The gate length on ST’s 20nm/14nm process is 18nm.

Interestingly, it transpires that TSMC’s 16nm process was so named because 14 is an unlucky number in Chinese.

So much for science.

Tags: chery, Intel, jean marc, teeth, unlucky number

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3 Comments

  1. david manners
    May 20, 2013 10:44

    Of coursde you’re absolutley right Mike, the number on the process node has been disconnected from the gate length for years. But that’s really my point – these companies (or more likely their PR departments) go spraying around numbers for nodes which are essentially meaningless. I didn’t know of this measurement bassed on a 6T SRAM cell. If everyone uses it OK, but I rather suspect that some manufacturers will prefer the system we have now – think of a number and slap it on the node. After all, the proof of the process will be in the characteristics of the ICs.

  2. Mike Bryant
    May 19, 2013 19:21

    For the umpteenth time the node has not defined by the gate length since before 90nm. Contacted gate length is the key measure for density and this is from 3 to 5 times the gate length depending on the process. In fact anyone could make their gate length shorter at any node but the performance would be rubbish if you haven’t got the appropriate contact and channel engineering.

    Most people (but obviously not J-MC) use the area of a standard power 6T SRAM cell divided by a constant independent of process or node. The Intel one is 22.6nm and the last figure I saw for ST FD-SOI process made it a 27.8nm process.

    However this could fall down later with the new 14nm transistors with 20nm BEOL processes at TSMC and GF. We’ll have to wait and see on that one.

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