Ruminations on the electronics industry from David Manners, Senior Components Editor on Electronics Weekly.
TSMC not following Intel to Finfets at 22nm – waiting till 20nm.
TSMC will not move to Finfets until the 20nm process generation.
Now that Intel has declared it is putting Finfet transistors into production on a 22nm process later this year, the question arises: how far are the other companies behind?
Nearly a decade ago, TSMC demo-ed a 0.25 micron Finfet – what Intel calls a Tri-Gate – transistor.
TSMC actually hired FinFET co-inventor Chenming Calvin Hu to develop TSMC’s proprietary FinFET.
However TSMC now says that it does not intend to use Finfets until the 20nm process generation when it feels planar transistors will run out of poke.
Finfets are a way to get more performance out of a transistor without having to increase the input power. This makes Finfets a way round the leakage problem.
Last year TSMC said it had developed a complete high-performance 22/20nm CMOS logic process using FinFet transistors.
The process was used to build a 0.1µm2 SRAM memory cell which had 90mV noise at a 0.45V operating voltage.
However TSMC is not moving on Finfets until it feels the design and layout tools are mature – which they are not at the moment.
Intel is under pressure to reduce the power of its mobile chips to compete with ARM and Finfets are seen as a way to do that. 22nm Tri-Gate transistors are said to either deliver up to 37% more performance at the same voltage as Intel’s 32nm planar transistors, or to use less than half the power while delivering the same performance.
At Europe’s leading microelectronics research establishment, Imec, Luc van den Hove, the President of Imec, told us last year: ”Around 20nm is when we’ll consider 3D devices like Finfets and multi-gate transistors – at 15nm they’ll be used for sure.”
Apart from FinFets, other exploratory concepts being pursued in transistor design are: Quantum Well devices; Tunnel FET; Graphene FET; and Carbon Nanotubes.
GloFo is in a bit of a fog about it all, rambling: ”We and our development partners have longstanding programs to evaluate options for next-generation transistors, including non-planar structures, and we don’t see the need for these technologies until beyond the 22/20nm generation.”
Over two years ago, IBM, Applied Materials and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany announced an agreement to co-develop Finfet technology for manufacturing 22-nm logic and memory chips.
At that time it was said that Finfets were considered a potential successor to planar transistors for 22-nm chips.
However Finfets may be shortlived. Finfet co-inventor Professor Tsuâ”Jae King Liu of the University of California at Berkeley says that, for post-22nm processes, Finfets may not produce better performance than planar transistors.Tags: layout tools, luc van, microelectronics research, transistor design, tsmc