Embedded designers need responsiveness, low-latency and determinism, while processing designers need throughput and raw computing power. Most products attempting to bridge these domains end up dissatisfying both and not adding to the art.
The ‘proper’ answer is to provide raw computing power that is tightly coupled to the outside world through an intelligent channel and port structure.
Imagine a 450Mips microcontroller that has multi-threading, hardware scheduling, an event-driven architecture and intelligent I/O management. This takes important steps toward satisfying the requirements of different design camps.
But wonderful silicon is only part of the answer – you also need flexible and accessible tools that permit easy access to the capabilities of the chips. Abstraction must not only make it easier to conceptualise the application, it must also map gracefully into the target silicon resources with minimal effort. This is not a trivial development exercise, but absolutely necessary to make a successful entrant product into this domain.
For some time I have been advocating an approach that takes this new way of looking at programmable silicon to a different level. XMOS is developing something in this area called software defined silicon (SDS). It provides not only software programmability, but also hardware reconfigurability through an event driven, multi-threaded processor array on a single chip that has the performance and flexibility for the next generation of industrial and consumer designs.
Upgrading and evolving a product often requires the addition of new silicon devices on the PCB which brings with it significant verification work. Being able to modify the features of a system without changing the physical hardware design is valuable in saving time and money. The benefits of developing multiple products from a single hardware platform using a firmware change to add, remove or modify features are well known, however this has previously been too expensive for high volume products.
SDS differs from existing technologies by taking an entirely software approach to providing configurability and programmability. It uses small arrays of processors instead of large arrays of gates with the benefit that the silicon area and hence cost is dramatically reduced. This is a departure from classic multi-core designs that end up being much larger than projected due to the demands of shared memory and interconnect.
A key challenge is the ability to implement traditional hardware tasks using software.
Interfaces such as Ethernet have been historically difficult to do in software; they require pins to be controlled in a hard real time environment. The designer needs to be able to guarantee that the software will service the I/O pins no matter what other software is running.
Implementation of multiple interfaces in software raises another challenge – that of parallel programming. The software must be capable of switching context fast enough to allow multiple tasks to run simultaneously.
Until now these challenges have kept processors and software away from efficiently and successfully describing interfaces and hardware blocks. SDS solves these problems and, as a result, many systems can now be entirely defined using software. This gives the designer a new degree of freedom, flexibility and creativity.
The multi-core use of modest processors may seem counter to industry trends that strive for ever-faster, ever-bigger processing elements. While high-end compute engines have their place, many applications are more appropriately implemented in moderately powerful processors, with intelligent communications and multi-core architectures.
David May is chief technology officer at XMOS Semiconductor