Designing with synchronous DC-DC converters from Panasonic

The transient performance and frequency stability of hysteretic-based synchronous DC-DC converter ICs can be improved with ramp control and adaptive on-time techniques.

The control method used in a line-up of high current synchronous buck DC-DC converter ICs with integrated FETs by Panasonic meets the challenges of high efficiency under low and high load currents, superior load transient performance and simplified power circuit design required by state of the art digital control circuits using ICs operating with low supply voltages.

Besides the power efficiency, a key performance requirement for point of load power supply ICs is the transient performance. Sudden changes in the current drawn by the load, e.g. with an FPGA, require a fast response from the power supply.


Fig 1: Simplified Diagram Representing Output accuracy at low voltage

Such fast variations of the output current however cause transient spikes on the output voltage, whose amplitude and duration depend on the transfer function of the regulation loop.

The increasing degree of miniaturization of semiconductor processes results in lower breakdown voltages of the transistors, and therefore lower supply voltage levels. This in turn reduces the available margin for transient over- and under-voltages on the device’s supply rails.

An overshoot above the process’ breakdown voltage can cause the destruction of the device, on the other hand an undershoot below the device’s minimum operating voltage can cause a malfunction (see figure 1b).

Power supply ICs featuring a good load transient performance and a high efficiency ensure sufficient margin to easily design safe power supply circuits while contributing to power savings. Panasonic’s control method used in a new line-up of high current buck DC-DC converter ICs addresses both challenges.

Voltage mode vs. current mode vs. hysteretic control

Let’s review some control schemes commonly used in DC-DC controllers in terms of load transient accuracy and compensation techniques.


Fig 2: Voltage mode control block diagram.

A typical voltage mode controller monitors the output voltage Vo from a single feedback path and compare it with a reference voltage at an error amplifier. In a second step a PWM is generated by comparing the error signal with a saw-tooth waveform. The PWM is used as input signal to drive the control FET, as shown in the figure 2.

A drawback of the voltage mode control is that a compensation network is required to improve the phase margin of the closed control loop, ensuring the stability of the power supply. As a result, a larger PCB area is needed for the external compensation circuit.

Furthermore, the compensation network and the amplifier slow down the feedback loop’s response.

The designer often needs to trade off stability for transient response, which can be complicated to optimize. Therefore, the conventional voltage mode control is not the most convenient solution for fast load transient applications.

A current mode controller consists of 2 loops. An outer voltage control loop tracks Vout. An inner loop tracks the inductor current IL by the sense resistor RS and generates the reference signal used by the PMW generator (see figure 3).

The current feedback loops eliminates a complex pole introduced by L & CO in the closed loop transfer function, and simplifies the loop compensation. This effectively allows the current mode control to be faster than the voltage mode.

Moreover, it is easier to use than voltage mode control, as it requires less external circuitry.


Fig 3: Current mode control block diagram

However, the current sense resistor affects the efficiency of the system. The current sense loop is also subject to switching noise when the inductor current transits between the low side (represented as a diode in the fig. 3) and the high side power switches.

Usually, more complicated methods of current sensing needs to be implemented, increasing the complexity of the controller, which results in a larger silicon area and a higher cost.

Conventional hysteretic control (see figure 4) is the simplest method, as the feedback loop does not require any compensation.

The output voltage is kept within a hysteresis window, defined by a reference voltage. The output of the hysteretic comparator turns the main switch Q1 ON/OFF.

This method’s transient response is the fastest as compared with the voltage mode and current mode, because the transient response time depends only on the delays in the hysteretic comparator and in the driver circuitry.


Fig 4: Conventional Hysteretic mode control regulator and waveforms

This method however imposes a ripple on the output voltage, corresponding to the width of the comparator’s hysteresis. The ripple is produced through the ESR (Equivalent Series Resistance) of the output capacitor CO, and is desired to be small.

The ripple can be reduced by decreasing the hysteresis width, however there is a design trade-off, as this causes the switching frequency to be higher and the operation to be unstable at some point. At the same time the switching frequency is a function of VIN, VO, L, CO and of the width of the hysteresis window.

This poses serious challenges to the designer for the selection of the external components, and limits the use cases of this method.

Control method from Panasonic

Building on the hysteretic approach, an enhanced controller for a synchronous power conversion circuit is introduced that overcomes the drawbacks of the conventional method.

The output ripple is suppressed, yet a fast transient response is maintained, noise robustness is ensured, the design is simple with no compensation components necessary, and the method allows user-selectable, stable operating frequency operation.

Ramp control technology (virtual ripple generation)


Fig 5: Panasonic hysteretic-based control block diagram

As shown in the figure 5, a ramp wave equivalent to the output ripple voltage of a conventional hysteretic controller operating under the same conditions is superimposed to the reference voltage.

This internally generated “virtual ripple” ensures a sufficient hysteresis width at the comparator while allowing the actual output ripple to be minimized.

As the external ripple is reduced and no compensation circuit is required under this control scheme, the number of necessary external components is kept to a minimum, and the coil can be under-dimensioned as compared with other control methods.

This circuit configuration and operating waveforms are shown in figure 6. The output detection voltage Vfb, copied from Vo through a resistive divider, is fed back and compared to the reference voltage Vref to which the ramp wave is added.

When the output detection voltage Vfb equals to the increasing reference voltage Vr while the main switch Q1 is off, the comparison result Vc is reversed and the main switch Q1 is turned on. At this time, a timer used to fix the on time for that period starts counting.

Adaptive on-time control


Figure 6: Ramp control method

Following the comparator, an adaptive on-time controller sets the ON time of the control switch Q1 to a fixed value at each switching period based on the output voltage, the input voltage, and the operating frequency set by the user. The on-time Ton is specified as the equation (3) using the target period Tsi set by the user. Q1 is turned OFF after the determined on-time elapses.

This approach ensures that the DCDC can operate at stable, selectable switching frequencies, even using the simple comparator concept described in the previous paragraphs.

Improved noise margin

The figure 7 shows another beneficial side-effect of the ramp control technology. LX is the switching node connected to output inductor in figure 5. Every time the LX switches, noise is injected to the DC-DC system.

For adaptive on time systems, the noise is critical during LX low to high transition because only the on time is fixed, so the noise injected to the feedback loop can cause multiple LX switching (unstable switching).


Figure 7: Low noise margin with ramp control technology


The ramp control introduces a negative offset naturally synchronized with the low to high transitions of LX, which improves the system noise margin.

Summary of advantages

The improvements in response speed and precision brought by Panasonic’s control method are illustrated in the figure 8.

The patented combination of ramp control technology with adaptive ON time control is Panasonic’s original method that enables high efficient integrated DC-DC ICs featuring:

  • Fast response,
  • Increased safety margin under low Vout and high load current,
  • Stable operation at fixed controlled switching frequency,
  • Robustness to noise,
  • Easy design of the power supply circuit,
  • Reduced bill of material.

Panasonic has developed a line-up of DC-DC buck ICs with built in FETs using the original control method presented in this article.


Figure 8: Panasonic performance versus conventional performance

Various options of input voltages between 4,5V and 30V, output voltages between 0,6V and 5.5V and output currents between 3A and 10A in very small 4x4mm² and 6x6mm² power QFN packages target POL application and PCB power supply for embedded computing, telecom equipment, set top boxes, monitors and TVs, storage devices (SSD/HDD), building and security systems.

Panasonic MCP DC-DC switching regulators combine in small multi-chip QFN packages an ultra-fast and accurate transient behaviour, high efficiency thanks to FET drivers optimised for the built-in, Panasonic’s own, low Ron trench MOSFETs, a selectable frequency operation, a complete range of state of the art safety features,.

Designers can enjoy ease of design, smaller overshoots and undershoot in response to sudden change in load current, better noise immunity, a reduction of the PCB area and of the bill of material.

Writers are Joel Tang, design engineer – mixed signal IC design and Keng Hoe Tee, application engineer – global solution engineering at Panasonic Industrial Devices Semiconductor Development Asia.


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