Toshiba has announced at the PCIM exhibition in Germany a new generation of superjunction (SJ) technology for power mosfets.
The new DTMOS-IV process, which is being deployed in the company’s latest family of high-speed, high-efficiency 600V power mosfets, offers on resistance ratings that are up to 40% lower than first-generation DTMOS products for the same die size, said the supplier.
For example, a 600V mosfet in TO-220SIS package has an RDS(ON) of 0.065?, or a similar device in a TO-3P(N) package has an RDS(ON) down to 0.04?.
The DTMOS-IV technology uses a deep-trench filling process that results in a narrowing of the lateral superjunction pitch, leading to optimised overall performance.
This allows Toshiba to minimise mosfet output capacitance (Coss) for optimised SPS operation at light load.
“An optimised gate-drain capacitance delivers improved dv/dt switching control, while an optimised RDS(ON) Qg figure of merit supports high-efficiency switching,” said Toshiba.
The first MOSFETs to be based on DTMOS-IV are available now in an expanded line-up that comprises DPAK, IPAK, D2PAK, I2PAK, TO-220, TO-220SIS, TO-247, TO-3P(N) and TO-3P(L) packages.
The mosfets are expected to be used in switch mode power supplies, lighting ballasts and other power applications that demand a combination of high-speed operation, high-efficiency, and low EMI noise.