28nm is fabulous for Xilinx, says Gavrielov.
28nm is turning out to be a great node for Xilinx. “It is absolutely fabulous for us,” Xilinx CEO Moshe Gavrielov tells EW, “it’s the node which is getting us the fastest number of design wins and transferring to revenue quicker than any other node. We’re shipping $10m in Q2. I expect it will be the largest node ever for our business.”
“The amount of design wins and early adoptions are ahead of where we expected them to be,” says Gavrielov.
“We’re definitely ahead of plan in terms of yield,” adds Gavrielov, “we’re not seeing yield issues on HPL. It’s a high K metal gate process but it’s a less complex process than the HP process – it has less mask steps.”
He attributes the high yields to the “very intimate” linkage in process development with TSMC and to the decision Xilinx made to use TSMC’s HPL process rather than the LP and HP processes chosen by companies which have struggled.
He adds that there are aspects of the HP process which Xilinx’s engineers considered to be riskier than the HPL process.
“We dodged some of the challenges other companies have encountered,” says Gavrielov.
Nvidia, Qualcomm and Altera have all complained about shortages of supply from TSMC.
Gavrielov concedes that: “TSMC may have under-estimated capacity requirements but they’re scrambling to fix that.”
Xilinx has just started sampling its 28nm heterogeneous 3D stacked Virtex-7 and is shipping volume ‘thousands of units’ of its homogeneous 3D stacked part.
Homogeneous means it only has FPGA slices; heterogeneous means it has FPGA slices plus transceivers.
The Virtex 7 has16 28Gbps transceivers and 72 13.1Gbps transceivers. The die sit side by side on an interposer connected by TSVs.
“It has much higher bandwidth than you can achieve with an FPGA,” says Gavrielov.
Xilinx’s high hopes for the 3D part derive from the tools.
“It’s not just the TSVs and it’s not just the architecture of the silicon or the packaging – the big enabler is the software,” says Gavrielov, “that’s why we’re so excited by Vivado (the design suite) – because we have a unique advantage because we provide the tools. Vivado’s taken 1000 man-years to develop. With the tools you can achieve things which would be very difficult to do with commercial tools. We provide Vivado to customers as a cost of doing business. Anyone who buys the chip gets the software.”
“In July, Vivado will be made broadly available to our entire customer base.”
When it is made broadly available, Vivado will include the tools for programming FPGAs in C. Xilinx acquired the technology when it bought AutoESL.
Do customers use it? “Absolutely,” replies Gavrielov, “they’re getting fabulous results. They’re getting results which customers say are better optimised than hand-crafted designs.”
“It’s revolutionary in terms of time to market and it broadens the markets we address,” says Gavrielov, “it allows a lot of designers who are not FPGA heavyweights to use FPGAs. It allows other designers to get the benefits of an optimised FPGA solution. So it broadens our user base.”
The C programmable tool works for all Xilinx’s parts at the 28nm node and will be integrated into the Vivado programme when it goes to all Xilinx’s customers in July.
Another thing which 28nm brings to the party is low-cost SOC. Here the company has come out with Zynq which has a brace of ARM Cortex A9s, DSPs, and virtually any peripheral you want.
“It’s the biggest deal,” says Gavrielov, “it allows us to move full force into SOC. It’s low power, it’s low cost it has all the advantages of SOC design without the cost. Moving to 28nm means we can do amazing things – it’s an SOC but it’s all programmable – the software, the hardware and the I/O.”
“It could be done in the past but it was too expensive,” adds Gavrielov, “now, with 28nm, we can attack a lot of applications head on. For instance automotive is very cost-conscious. We couldn’t get within a hundred miles of an automotive SOC. Now we can.”
“At 28nm we’re taking a lot of share from ASICs and ASSPs,” concludes Gavrielov, “we expect the FPGA market to continue to grow faster than the ASIC and ASSP markets. We expect market growth of 8-12% CAGR between 2011 and 2020 – so by 2020 it should have doubled in size from today’s $5bn.”