Data transfer is at 11.6Gbps by integrating two 5.8Gbps MIPI M-PHY HS-G3 I/F data lanes – an optional feature of UFS Ver. 2.0.
The modules have read speeds of 650MB/s and write speeds of 180MB/s.
The modules are sealed in a 153 ball FBGA package measuring 11.5mm x 13.0mm x 1.0mm for the 32GB die and 11.5mm x 13.0mm x 1.2mm for the 64GB die and have a signal layout compliant with JEDEC UFS Ver.2.0.
The modules are rated for an operating temperature of -25°C to +85°C and support memory core voltages of 2.7V to 3.6V.
Demand continues to grow for large density, high-performance chips that support high resolution video, driven by improved data-processing speeds in host chipsets and wider bandwidths for wireless connectivity in a wide range of digital consumer products, including smartphones and tablet PCs.
The JEDEC UFS Ver.2.0 compliant interface handles essential functions, including writing block management, error correction and driver software. It simplifies system development, allowing manufacturers to minimize development costs and speed up time to market for new and upgraded products.
Toshiba reckons its first to sample modules in this format and will move to mass production as demand dictates.