The Denali DDR4 consists of a DDR PHY and controller which supports per-bit de-skew capability and low-jitter phase-locked loops (PLLs).
Compatibility to DDR3 and DFI 3.1 standards ensures interoperability with other IP and allows for multiple memory types to be used within the same design.
The HSIC PHY IP is a mixed-signal transceiver macro-cell that implements the USB 2.0 HSIC layer for USB 2.0 high-speed device and host applications. The integrated solution made up of the Cadence HSIC PHY interface with the STMicroelectronics HSIC PHY I/O features extremely low power consumption and silicon area.
Cadence has qualified its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process, including Cadence Encounter, Digital Implementation System, Interactive Physical Verification System, QRC Extraction Solution, Tempus Timing Signoff Solution, Spectre Simulator, Virtuoso Schematic Editor, Virtuoso Analog Design Environment, and Virtuoso Layout Suite.
"Companies looking to take advantage of the performance and power benefits of 28nm FD-SOI need to know that they also have the IP solutions and tools that are qualified for the process," said Cadence's Martin Lund, "from early on, Cadence has worked with STMicroelectronics on FD-SOI technology and can assure our customers that they can quickly implement these IP solutions and sign off their designs."
"FD-SOI technology delivers superior energy efficiency at the 28nm node and allows for a wider range of dynamic voltage and frequency scaling, leading to higher processing power per watt, lower thermal dissipation, and extended battery life for portable devices," said ST's Philippe Magarshack, "having just announced a leading foundry partner and now adding prominent IP and EDA suppliers like Cadence expands the growing ecosystem, for the benefit of our mutual customers and the entire electronics industry."
Cadence will present its design IP at CDNLive in Munich (19-21 May).