ESiP was funded by public authorities of nine countries and the ENIAC Joint Undertaking. The German Ministry of Education and Research (BMBF) was the largest contributor among the national ministries.
System-in-Package means different types of chips made using different production techniques and structure widths are embedded side by side or stacked above one another in one chip package.
Technologies for combining chips in SiP packages and manufacturing them were developed and procedures for measuring reliability and methods as well as equipment for failure analysis and testing were developed.
Basic technologies were developed that enable the integration of various types of chips in the smallest volume of an SiP package, for example, customer-specific processors with the latest CMOS technologies, light-emitting diodes and DC-DC converters, MEMS and sensor components and passive components such as miniaturized capacitors and inductors.
New production processes for SiPs were developed and new materials for building SiPs were investigated.
The feasibility and reliability of the production processes have been proved with more than 20 different test vehicles. New test flows, probe stations and probe adapters were developed for 3D SiP.
“The successful ESiP research enhances Europe’s position in the development and manufacture of miniaturized microelectronics systems,” says Infineon’s Dr. Klaus Pressel.
Half of the €35m budget was financed by the 40 project partners. Of the other half two thirds were provided by national funding organizations in Austria, Belgium, Finland, France, Germany, Great Britain, Italy, the Netherlands and Norway, and one third by the European Union through its ENIAC Joint Undertaking.
In Germany, the BMBF sponsored the ESiP project as part of the Information and Communications Technology 2020 programme (IKT 2020) to the tune of around €3.1m, along with funding from the Free State of Saxony.