The 16FF DDR4 PHY IP operates at up to 3.2Gbps, a 50% increase in speed over previous generation DDR3 IP, while reducing power by 25% at the same speed.
On TSMC’s 16FF process it achieves 3.5Gbps speed on the external loopback test and running write/read operation up to 2.7Gbps with a 2.4Gbps DDR4 DRAM successfully.
The 16FF DDR4 IP features a DRAM link up and 40 percent core power reduction at the same speed compared to DDR3 IP on 28nm technology. P
The 16FF DDR4 IP is built in a PHY training mode that easily boots, saves evaluation time and optimizes data strobe positioning. Specifications used for the test chip also called for the use of ASE’s Flip Chip package (FCBGA) and multi-layer build up substrate manufactured by Nanya PCB. The new IP targets a variety of high-speed networking and server applications.
“This 16FF DDR4 IP represents an early opportunity for advanced technology designers to begin work on their next-generation devices,” says GUC President Jim Lai.