By optimizing the high-k/low-k/high-k stack, a program/erase window as large as 18V could be obtained, together with excellent retention and endurance. The novel three-layer inter-gate dielectric is scalable in thickness, allowing integration in tight pitch arrays. The result is promising for scaling NAND Flash memory below 20nm.
When scaling NAND Flash cells below the 20nm technology node, a fully planar architecture is required wherein the control gate is no longer wrapped around the floating gate because of too tight pitch. In such a planar structure, the program/erase window is however strongly reduced due to an important loss of the coupling factor. This window can be partially recovered by using a hybrid floating gate, where a high work function metal on top of the Si floating gate limits the leakage through the inter-gate dielectric during programming.
To further enlarge the programming window, Imec has successfully combined such a hybrid floating gate (2nm Si/5nm TiN) with a three-layer inter-gate dielectric structure made of high-k/low-k/high-k materials. This combination of materials further limits the inter-gate dielectric leakage and, at the same time, increases the coupling ratio, allowing for further voltage scaling. The best results were obtained with a 10nm HfAlO/5nm Al2O3/10nm HfAlO stack with amorphous middle Al2O3 layer. With this structure, a program/erase window as large as 18V could be obtained. This is a huge improvement w.r.t. a single Al2O3 dielectric layer. Also, retention tests show negligible charge loss at bake temperatures as high as 125°C.
Key to these results are the good morphological properties of HfAlO, and its good stability with TiN. In addition, the HfAlO/Al2O3/HfAlO stack can be scaled down to 10nm/5nm/5nm with only ~1V loss in program window and ~2V in erase window, but with a gain of 1V in program/erase voltages. The scaled down version still shows very good retention and endurance. This scalability in thickness is important for further program voltage scaling, which requires a lower equivalent oxide thickness of the inter-gate dielectric. These developments will largely contribute to the scaling of NAND Flash memory below 20nm.