The 32-bit VLIW DSP embeds Fmax tracking and operates at 460MHz at 397mV and 2.6GHz at 1.3V.
The device, produced by ST in their 28nm UTBB fully depleted SOI process technology, allows body-bias-voltage scaling from 0V to +2V, decreases minimum circuit operating voltage, and supports clock-frequency operation of 460MHz at 400mV.
The demonstrator achieves UWVR, greater energy efficiency, and unprecedented levels of efficiency in voltage and frequency using a combination of design techniques.
ST and Leti developed and optimized standard cells libraries over the 0.275V-to-1.2V range: they offer ideal implementation results by virtue of non-overlapping power-performance characteristics. Among the optimized cells, fast pulse-triggered flip-flops are designed for variability tolerance at low voltage.
Additionally, on-chip timing-margin monitors dynamically adjust the clock frequency to a few per cent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology. As a result, even at 0.4V, the DSP exhibits 10x state-of-the-art operating frequency.
"UTBB FD-SOI technology is ST's faster, cooler, simpler solution," says ST evp Philippe Magarshack "it delivers significant improvements in performance and power savings while minimizing adjustments to existing design and manufacturing methodologies. This demonstration DSP shows that FD-SOI is blazing the trail for better portable and battery-powered products, using more efficient semiconductor chips, all the way down to the 10nm node."