IEF2013: Liars’ contest on nodes, says Mentor CEO.
Rhines told the IEF2013 meeting in Dublin that the progress of Moore’s Law, which Means transistor cost declined 30% every 18 months, and the dictates of the learning curve which meant that a doubling of the volume reduced the cost by 30%, meant thst process became all-important in the semiconductor business.
“Feature size became the metric of success, ” said Rhines, “then the hype started. There was the DRAM gate length, there was the actual gate length. The marketing departments came in and the claims got out of control on gate length.”
“Then they called in the referee in 1994 – the ITRS,” continued Rhines, “and they developed rules that volume is 10,000 units a year and minimum feature size – usually the poly gate – is the measurement.”
“Then the logic people asked for a separate rule and they took the first production shipment for logic.”
“The liars’ contest had to begin again,” said Rhines.
At 90nm Samsung actually had a 90nm gate length and at 70nm AMD erred on the side of conservatism by actually having a 35nm gate length, but then TI called a process 65nm where the the smallest gate was 130nm.
“At that point the ITRS said: ‘We give up’,and said it would make no more references go technology nodes,” said Rhines, “the ITRS told the industry: ‘You’re on your own’.”
“TSMC had a 20nm process on their technology roadmap. They asked themselves: ‘What to we call it?’ and called it a 16nm process,” said Rhines, “GlobalFoundries have a 20nm process.they asked: ‘What do we call it?’ and answered: ‘Ah Yes – 14nm’.”
The day before at IEF2013, Penn had said: “The current spin and hype is out of control, the industry needs to come out with a definition of what a process is.”