Leti: 450mm wafers essential below 7nm

Economics will dictate a move to 450mm wafers for chips with features below 7nm, according to French semiconductor research lab Leti .


“We think economics is not an issue down to 10nm, or probably 7nm, then you will need 450mm,” said Leti CEO Laurent Malier.

He is looking into the future, where the laws of physics make smaller transistors difficult, and the cost of masks and lithography is becoming prohibitive.

Finfets, championed by Intel amongst others, are one way to make viable transistors in smaller sizes. Planar fully-depleted silicon-on-insulator technology – backed by Leti, STMicroelectronics, IBM and Global Foundries – is the other big option, although currently less favoured than finfet.

Between the two, finfet has had more development, uses simple silicon wafers, and delivers plenty of drive current, at the cost of complex 3D processing. FD-SOI requires expensive SOI wafers, but only simple planar processing, and doesn’t need high drive current.

Which approach will be most effective for which applications is not yet clear.

Both technologies have small features, and small features demand either multiple patterning, requiring multiple sets of expensive masks, or a move to EUV lithography, which will cost a great deal and is proving difficult to get working.

Against this, the expensive and difficult move to 450mm wafers could bring the cost per chip down because twice the number of chips are made per wafer processing step.

“The cost of development of each technology and design platform is high. Finfet has been a huge step. The cost of each design, with its masks etc., is increasing, and clearly EUV is very costly,” said Malier. “I think 7nm will exist, my guess is on 300mm. It will probably be a mixture of 300 and 450mm. My guess is, for certain applications, wireless is one, a few players like Samsung and Qualcomm can afford to design even if it is very expensive.”

For everyone else: “Having affordable 28, 20 and 14nm nodes is a long-term state for the industry. For the Internet of chips you will not need the most aggressive node. For power efficiency it will be 28nm, for cost efficiency possibly 14nm when high volume has driven the cost low.”

With processes shrinking slower than Moore’s Law, 3D integration is one way to get more transistors into the same package.

“3D will play more and more: through-silicon vias, interposers, and MEMS.”


“There is some interest from foundries. 3D in big fabs will make some processes available that could be used for MEMS,” said Malier.

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