Samsung Electronics has qualified 32nm low-power (LP) process with high-k metal gate (HKMG) technology.
The 300mm wafer line at the S Line, in Giheung, Korea is ready for production of customer designs, said Samsung.
The 32nm LP HKMG gate-first process was developed as part of the IBM Joint Development Alliance.
“Congratulations to Samsung on being the first foundry to demonstrate SoC’s using high-k/metal gate technology,” said Gary Patton, v-p for IBM’s Semiconductor Research and Development Centre.
Samsung has manufactured a 32nm LP ARM 1176 core-based system-on-chip (SoC) that shows 30% dynamic power reduction and 55 percent leakage power reduction when compared to the SoC design implemented at 45nm LP at the same frequency.
Samsung’s EDA partners include Synopsys, Cadence Design Systems and Mentor.
According to Digitimes, Samsung has a plan to aggressively expand its foundry capacity from its current 27,000 eight inch equivalent wafers a month to 40,000 by the end of the year, to 125,000 by the end of next year and to 200,000 by the end of 2012.
This, of course, is a long way behind market leader TSMC’s 10m eight inch wafer equivalent capacity a year. Nor does Samsung appear to have a strategy to build 100,000 wafer a month GigaFabs to acquire the same economies of scale as TSMC.