Mentor’s common verification environment
Verification is moving from the lab to the data centre as SOC designs require system-level verification which brings the need to unify pre-silicon verification and post-silicon verification, says Wally Rhines, CEO of Mentor Graphics.
“We need to move from the lab to the datacentre,” says Rhines, “there’s a need for an enterprise-level solution. In a word, you need a common environment.”
That means common debug, common verification IP, common user interface, common testbench stimulus, common assertions and common coverage.
Mentor, which dominates verification, is best placed for the challenge.
“Verification is almost a billion dollar market,” says Rhines, with simulation and emulation the fastest growing segments of the EDA industry.
Simulation is a $486 million market segment growing at 7% CAGR, emulation is a $363 million segment growing at 39% CAGR and formal is a $135 million segment growing at 11% CAGR.
“Emulation is becoming mandatory for system-level verification,” says Rhines, adding
“Mentor’s emulation revenues have grown at 30% CAGR from 2010 to 2014.”
So, in late Q2, Mentor’s response to the unification challenge will be available with its
Enterprise Verification Platform (EVP), which combines Questa verification, Veloce OS3 emulation, and Visualizer debugging into a datacentre resource.
EVP, says Mentor, delivers performance and productivity improvements ranging from 400X to 10,000X.
“Mentor’s verification vision is to deliver an environment where the verification process is completely abstracted from the underlying verification engines from first design thoughts, through silicon, to final product,” says Mentor’s John Lenyo, “with EVP, Mentor has eliminated the barriers to hardware acceleration and ushered in a new era of enterprise-level verification that combines the functionality and observability of simulation-based verification with the speed of emulation.”