Planar 20nm may not suit mobile, says GSS
The problems with planar scaling to 20nm may make it unsuitable for mobile applications, according to Professor Asen Asenov, Professor at Glasgow University and CEO of Gold Standard Simulations (GSS).
“My understanding is that 20nm will be power hungry node and only big players with high performance products will consider it,” Asenov tells EW, “the rest will stay with 28nm as long as possible, or until better FinFET options become available.”
Despite many announcements of key foundry players regarding FDSOI and FinFETs, unless you are Intel, bulk CMOS remains the only certain option for the majority of fabless companies at 20 nm.
GSS decided to investigate how the statistical variability, which is an inherent weakness of 28nm bulk CMOS, worsens as the technology shrinks to 20nm, thus further compromising design margins. The investigation includes a direct comparison of “metal gate first” and “metal gate last” technology.
At 20nm metal-gate-last could buy you 100mV reduction of the SRAM Vcmin compared to metal-gate-first. “It is still not clear that everyone will do gate last at 20nm,” says Asenov, “there are still discussions in the common platform related to cost.
The basis for this comparison is a template MOSFET with 25nm physical gate length typical for high-performance transistors at 20nm CMOS. The transistors were carefully designed using the GSS process simulator to meet the requirements of the ITRS and the expected performance to be offered by leading foundries. The doping design is optimised to reduce the statistical variability, keeping the doping concentration at the interface as low as possible.
Statistical CMOS variability is introduced by the atomicity of charge and granularity of matter. The main sources of statistical variability in bulk high-k/metal gate MOSFETs are random discrete dopants (RDD), line edge roughness (LER) and metal gate granularity (MGG). In metal-gate-first the implantation and activation of the self-aligned source and drain result in the polycrystalisation of the metal gate.
In the commonly used TiN metal gate the resulting average metal grain size is 5-6nm. It is believed that in the metal-gate-last technology the metal gate, deposited after the implantation activation will not suffer high temperature treatments and can be kept amorphous, thus eliminating MGG as a source of statistical variability.
The GSS study shows the magnitude of the statistical variability problem at 20nm CMOS.
The statistical variability has a dramatic impact on the SRAM cell design which utilises the small transistors in a CMOS circuit. In the presence of such large statistical variability it will be impossible to scale the SRAM by the traditional 50% in the transition from 28nm to 20nm CMOS.
Indeed at a recent tutorial at ESSDERC, it was hinted by Paul Zuber from IMEC, that the expected reduction in the SRAM area at 20nm would be approximately 40%.
Since the statistical variability scales as 1/(gate area) the impact on digital logic that uses wider transistors will not be so dramatic. Another sinister effect associated with the statistical variability results in approximately one order of magnitude increase in the average leakage current of a single transistor or in the overall leakage current of the chip compare to ideal transistors without variability.
.Although RDD remains the dominant source of variability in 20nm CMOS, the next most important source of statistical variability is the MGG. The elimination of the MGG as a source of statistical variability in the 20nm metal-gate-last technology results in approximately a 10mV reduction in the threshold voltage standard deviation.
This seemingly small reduction in the statistical variability has a dramatic impact, resulting in 100mV reduction in the SRAM Vcmin and a 50% reduction in leakage.
A more detailed report comparing the distributions of the various figures of merit of the 20nm CMOS metal-gate-first and metal-gate-last transistors is available for download from GSS.