TSMC has reference flows for 16nm finfet process.
TSMC has three silicon-validated Reference Flows for 16nm finfet processes and through-transistor stacking for 3D packaging.
There is a 16Finfet Digital Reference Flow offering design support including addressing extraction, quantized pitch placement, low-vdd operation, electromigration, and power management.
Second, there is a 16Finfet Custom Design Reference Flow offering full custom transistor-level design and verification including analogue, mixed-signal, custom digital and memory.
The third flow is a 3D IC Reference Flow for 3D stacking.
EDA vendors worked with TSMC to validate all three flows with multiple silicon test vehicles.
“These Reference Flows give designers immediate access to TSMC’s 16Finfet technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology,” says TSMC vp of R&D, Dr. Cliff Hou, “delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners.”
The 16Finfet Digital Reference Flow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification.
It helps designers adopt the new technology by addressing Finfet structure related challenges of complex 3D Resistance Capacitance (RC) modelling and quantized device width.
In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route (APR).
The Custom Design Reference Flow enables custom design by addressing the growing complexity of 16FinFET process effects and provides methodologies for design compliance
The 3D IC process produces scaling, power and performance benefits by integrating multiple components on a single device.
TSMC’s 3D IC Reference Flow addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; TSV-to-TSV coupling extraction.